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arch-arm: Switch the AAPCS ABIs to .as<>() instead of .laneView<>().

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Change-Id: I9e9c7163db4c061af00111b8dc959c364c6b7ae6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41898
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-02-25 01:05:47 -08:00
parent ad204d9de0
commit 25ecaaadbe
2 changed files with 6 additions and 6 deletions
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8
src/arch/arm/aapcs32.hh
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@@ -463,7 +463,7 @@ struct Result<Aapcs32Vfp, Float, typename std::enable_if_t<
RegId id(VecRegClass, 0);
auto reg = tc->readVecReg(id);
reg.laneView<Float, 0>() = f;
reg.as<Float>()[0] = f;
tc->setVecReg(id, reg);
};
};
@@ -487,7 +487,7 @@ struct Argument<Aapcs32Vfp, Float, typename std::enable_if_t<
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
return val.laneView<Float>(lane);
return val.as<Float>()[lane];
}
return loadFromStack<Float>(tc, state);
@@ -558,7 +558,7 @@ struct Argument<Aapcs32Vfp, HA, typename std::enable_if_t<
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
ha[i] = val.laneView<Elem>(lane);
ha[i] = val.as<Elem>()[lane];
}
return ha;
}
@@ -605,7 +605,7 @@ struct Result<Aapcs32Vfp, HA,
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
val.laneView<Elem>(lane) = ha[i];
val.as<Elem>()[lane] = ha[i];
tc->setVecReg(id, val);
}
}

4
src/arch/arm/aapcs64.hh
View File

@@ -186,7 +186,7 @@ struct Argument<Aapcs64, Float, typename std::enable_if_t<
{
if (state.nsrn <= state.MAX_SRN) {
RegId id(VecRegClass, state.nsrn++);
return tc->readVecReg(id).laneView<Float, 0>();
return tc->readVecReg(id).as<Float>()[0];
}
return loadFromStack<Float>(tc, state);
@@ -203,7 +203,7 @@ struct Result<Aapcs64, Float, typename std::enable_if_t<
{
RegId id(VecRegClass, 0);
auto reg = tc->readVecReg(id);
reg.laneView<Float, 0>() = f;
reg.as<Float>()[0] = f;
tc->setVecReg(id, reg);
}
};