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dev: consistently end device classes in 'Device'

Browse Source 
PciDev and IntDev stuck out as the only device classes that
ended in 'Dev' rather than 'Device'.  This patch takes care
of that inconsistency.

Note that you may need to delete pre-existing files matching
build/*/python/m5/internal/param_* as scons does not pick up
indirect dependencies on imported python modules when generating
params, and the PciDev -> PciDevice rename takes place in a
file (dev/Device.py) that gets imported quite a bit.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Steve Reinhardt
2013-07-11 21:56:50 -05:00
parent 2737650a69
commit 502ad1e675
21 changed files with 88 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/arch/x86/interrupts.cc
View File

@@ -311,12 +311,13 @@ void
X86ISA::Interrupts::init()
{
//
// The local apic must register its address ranges on both its pio port
// via the basicpiodevice(piodevice) init() function and its int port
// that it inherited from IntDev. Note IntDev is not a SimObject itself.
// The local apic must register its address ranges on both its pio
// port via the basicpiodevice(piodevice) init() function and its
// int port that it inherited from IntDevice. Note IntDevice is
// not a SimObject itself.
//
BasicPioDevice::init();
IntDev::init();
IntDevice::init();
// the slave port has a range so inform the connected master
intSlavePort.sendRangeChange();
@@ -606,17 +607,17 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
}
X86ISA::Interrupts::Interrupts(Params * p) :
BasicPioDevice(p), IntDev(this, p->int_latency),
apicTimerEvent(this),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
pendingExtInt(false), extIntVector(0),
pendingInit(false), initVector(0),
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL),
intSlavePort(name() + ".int_slave", this, this)
X86ISA::Interrupts::Interrupts(Params * p)
: BasicPioDevice(p), IntDevice(this, p->int_latency),
apicTimerEvent(this),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
pendingExtInt(false), extIntVector(0),
pendingInit(false), initVector(0),
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL),
intSlavePort(name() + ".int_slave", this, this)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));

4
src/arch/x86/interrupts.hh
View File

@@ -72,7 +72,7 @@ namespace X86ISA {
ApicRegIndex decodeAddr(Addr paddr);
class Interrupts : public BasicPioDevice, IntDev
class Interrupts : public BasicPioDevice, IntDevice
{
protected:
// Storage for the APIC registers
@@ -215,7 +215,7 @@ class Interrupts : public BasicPioDevice, IntDev
void init();
/*
* Functions to interact with the interrupt port from IntDev.
* Functions to interact with the interrupt port from IntDevice.
*/
Tick read(PacketPtr pkt);
Tick write(PacketPtr pkt);

2
src/dev/Pci.py
View File

@@ -44,7 +44,7 @@ class PciConfigAll(BasicPioDevice):
class PciDevice(DmaDevice):
type = 'PciDevice'
cxx_class = 'PciDev'
cxx_class = 'PciDevice'
cxx_header = "dev/pcidev.hh"
abstract = True
platform = Param.Platform(Parent.any, "Platform this device is part of.")

8
src/dev/copy_engine.cc
View File

@@ -60,7 +60,7 @@
using namespace CopyEngineReg;
CopyEngine::CopyEngine(const Params *p)
: PciDev(p)
: PciDevice(p)
{
// All Reg regs are initialized to 0 by default
regs.chanCount = p->ChanCnt;
@@ -115,7 +115,7 @@ CopyEngine::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name != "dma") {
// pass it along to our super class
return PciDev::getMasterPort(if_name, idx);
return PciDevice::getMasterPort(if_name, idx);
} else {
if (idx >= static_cast<int>(chan.size())) {
panic("CopyEngine::getMasterPort: unknown index %d\n", idx);
@@ -680,7 +680,7 @@ CopyEngine::drain(DrainManager *dm)
void
CopyEngine::serialize(std::ostream &os)
{
PciDev::serialize(os);
PciDevice::serialize(os);
regs.serialize(os);
for (int x =0; x < chan.size(); x++) {
nameOut(os, csprintf("%s.channel%d", name(), x));
@@ -691,7 +691,7 @@ CopyEngine::serialize(std::ostream &os)
void
CopyEngine::unserialize(Checkpoint *cp, const std::string &section)
{
PciDev::unserialize(cp, section);
PciDevice::unserialize(cp, section);
regs.unserialize(cp, section);
for (int x = 0; x < chan.size(); x++)
chan[x]->unserialize(cp, csprintf("%s.channel%d", section, x));

2
src/dev/copy_engine.hh
View File

@@ -58,7 +58,7 @@
#include "sim/drain.hh"
#include "sim/eventq.hh"
class CopyEngine : public PciDev
class CopyEngine : public PciDevice
{
class CopyEngineChannel : public Drainable
{

4
src/dev/etherdevice.hh
View File

@@ -48,12 +48,12 @@ class EtherInt;
* The base EtherObject class, allows for an accesor function to a
* simobj that returns the Port.
*/
class EtherDevice : public PciDev
class EtherDevice : public PciDevice
{
public:
typedef EtherDeviceParams Params;
EtherDevice(const Params *params)
: PciDev(params)
: PciDevice(params)
{}
const Params *

8
src/dev/i8254xGBe.cc
View File

@@ -131,7 +131,7 @@ void
IGbE::init()
{
cpa = CPA::cpa();
PciDev::init();
PciDevice::init();
}
EtherInt*
@@ -151,7 +151,7 @@ IGbE::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
PciDev::writeConfig(pkt);
PciDevice::writeConfig(pkt);
else
panic("Device specific PCI config space not implemented.\n");
@@ -2453,7 +2453,7 @@ IGbE::ethTxDone()
void
IGbE::serialize(std::ostream &os)
{
PciDev::serialize(os);
PciDevice::serialize(os);
regs.serialize(os);
SERIALIZE_SCALAR(eeOpBits);
@@ -2507,7 +2507,7 @@ IGbE::serialize(std::ostream &os)
void
IGbE::unserialize(Checkpoint *cp, const std::string &section)
{
PciDev::unserialize(cp, section);
PciDevice::unserialize(cp, section);
regs.unserialize(cp, section);
UNSERIALIZE_SCALAR(eeOpBits);

16
src/dev/ide_ctrl.cc
View File

@@ -80,7 +80,7 @@ IdeController::Channel::~Channel()
}
IdeController::IdeController(Params *p)
: PciDev(p), primary(name() + ".primary", BARSize[0], BARSize[1]),
: PciDevice(p), primary(name() + ".primary", BARSize[0], BARSize[1]),
secondary(name() + ".secondary", BARSize[2], BARSize[3]),
bmiAddr(0), bmiSize(BARSize[4]),
primaryTiming(htole(timeRegWithDecodeEn)),
@@ -132,7 +132,7 @@ void
IdeController::intrPost()
{
primary.bmiRegs.status.intStatus = 1;
PciDev::intrPost();
PciDevice::intrPost();
}
void
@@ -157,7 +157,7 @@ IdeController::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC) {
return PciDev::readConfig(pkt);
return PciDevice::readConfig(pkt);
}
pkt->allocate();
@@ -232,7 +232,7 @@ IdeController::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC) {
PciDev::writeConfig(pkt);
PciDevice::writeConfig(pkt);
} else {
switch (pkt->getSize()) {
case sizeof(uint8_t):
@@ -523,8 +523,8 @@ IdeController::write(PacketPtr pkt)
void
IdeController::serialize(std::ostream &os)
{
// Serialize the PciDev base class
PciDev::serialize(os);
// Serialize the PciDevice base class
PciDevice::serialize(os);
// Serialize channels
primary.serialize("primary", os);
@@ -565,8 +565,8 @@ IdeController::Channel::serialize(const std::string &base, std::ostream &os)
void
IdeController::unserialize(Checkpoint *cp, const std::string &section)
{
// Unserialize the PciDev base class
PciDev::unserialize(cp, section);
// Unserialize the PciDevice base class
PciDevice::unserialize(cp, section);
// Unserialize channels
primary.unserialize("primary", cp, section);

2
src/dev/ide_ctrl.hh
View File

@@ -49,7 +49,7 @@ class IdeDisk;
* Device model for an Intel PIIX4 IDE controller
*/
class IdeController : public PciDev
class IdeController : public PciDevice
{
private:
// Bus master IDE status register bit fields

10
src/dev/ns_gige.cc
View File

@@ -146,7 +146,7 @@ NSGigE::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset < PCI_DEVICE_SPECIFIC)
PciDev::writeConfig(pkt);
PciDevice::writeConfig(pkt);
else
panic("Device specific PCI config space not implemented!\n");
@@ -2126,8 +2126,8 @@ NSGigE::drainResume()
void
NSGigE::serialize(ostream &os)
{
// Serialize the PciDev base class
PciDev::serialize(os);
// Serialize the PciDevice base class
PciDevice::serialize(os);
/*
* Finalize any DMA events now.
@@ -2298,8 +2298,8 @@ NSGigE::serialize(ostream &os)
void
NSGigE::unserialize(Checkpoint *cp, const std::string &section)
{
// Unserialize the PciDev base class
PciDev::unserialize(cp, section);
// Unserialize the PciDevice base class
PciDevice::unserialize(cp, section);
UNSERIALIZE_SCALAR(regs.command);
UNSERIALIZE_SCALAR(regs.config);

10
src/dev/pciconfigall.hh
View File

@@ -45,7 +45,7 @@
* PCI Config Space
* All of PCI config space needs to return -1 on Tsunami, except
* the devices that exist. This device maps the entire bus config
* space and passes the requests on to TsunamiPCIDev devices as
* space and passes the requests on to TsunamiPCIDevice devices as
* appropriate.
*/
class PciConfigAll : public BasicPioDevice
@@ -62,8 +62,8 @@ class PciConfigAll : public BasicPioDevice
/**
* Read something in PCI config space. If the device does not exist
* -1 is returned, if the device does exist its PciDev::ReadConfig (or the
* virtual function that overrides) it is called.
* -1 is returned, if the device does exist its PciDevice::ReadConfig
* (or the virtual function that overrides) it is called.
* @param pkt Contains information about the read operation
* @return Amount of time to do the read
*/
@@ -71,8 +71,8 @@ class PciConfigAll : public BasicPioDevice
/**
* Write to PCI config spcae. If the device does not exit the simulator
* panics. If it does it is passed on the PciDev::WriteConfig (or the virtual
* function that overrides it).
* panics. If it does it is passed on the PciDevice::WriteConfig (or
* the virtual function that overrides it).
* @param pkt Contains information about the write operation
* @return Amount of time to do the read
*/

22
src/dev/pcidev.cc
View File

@@ -53,7 +53,7 @@
#include "sim/core.hh"
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
PciDevice::PciConfigPort::PciConfigPort(PciDevice *dev, int busid, int devid,
int funcid, Platform *p)
: SimpleTimingPort(dev->name() + "-pciconf", dev), device(dev),
platform(p), busId(busid), deviceId(devid), functionId(funcid)
@@ -63,7 +63,7 @@ PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
Tick
PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
PciDevice::PciConfigPort::recvAtomic(PacketPtr pkt)
{
assert(pkt->getAddr() >= configAddr &&
pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
@@ -73,7 +73,7 @@ PciDev::PciConfigPort::recvAtomic(PacketPtr pkt)
}
AddrRangeList
PciDev::PciConfigPort::getAddrRanges() const
PciDevice::PciConfigPort::getAddrRanges() const
{
AddrRangeList ranges;
if (configAddr != ULL(-1))
@@ -82,7 +82,7 @@ PciDev::PciConfigPort::getAddrRanges() const
}
PciDev::PciDev(const Params *p)
PciDevice::PciDevice(const Params *p)
: DmaDevice(p), platform(p->platform), pioDelay(p->pio_latency),
configDelay(p->config_latency),
configPort(this, params()->pci_bus, params()->pci_dev,
@@ -150,7 +150,7 @@ PciDev::PciDev(const Params *p)
}
void
PciDev::init()
PciDevice::init()
{
if (!configPort.isConnected())
panic("PCI config port on %s not connected to anything!\n", name());
@@ -159,7 +159,7 @@ PciDev::init()
}
unsigned int
PciDev::drain(DrainManager *dm)
PciDevice::drain(DrainManager *dm)
{
unsigned int count;
count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
@@ -171,7 +171,7 @@ PciDev::drain(DrainManager *dm)
}
Tick
PciDev::readConfig(PacketPtr pkt)
PciDevice::readConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
@@ -210,7 +210,7 @@ PciDev::readConfig(PacketPtr pkt)
}
AddrRangeList
PciDev::getAddrRanges() const
PciDevice::getAddrRanges() const
{
AddrRangeList ranges;
int x = 0;
@@ -221,7 +221,7 @@ PciDev::getAddrRanges() const
}
Tick
PciDev::writeConfig(PacketPtr pkt)
PciDevice::writeConfig(PacketPtr pkt)
{
int offset = pkt->getAddr() & PCI_CONFIG_SIZE;
if (offset >= PCI_DEVICE_SPECIFIC)
@@ -343,7 +343,7 @@ PciDev::writeConfig(PacketPtr pkt)
}
void
PciDev::serialize(std::ostream &os)
PciDevice::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
@@ -351,7 +351,7 @@ PciDev::serialize(std::ostream &os)
}
void
PciDev::unserialize(Checkpoint *cp, const std::string &section)
PciDevice::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));

8
src/dev/pcidev.hh
View File

@@ -56,12 +56,12 @@
/**
* PCI device, base implementation is only config space.
*/
class PciDev : public DmaDevice
class PciDevice : public DmaDevice
{
class PciConfigPort : public SimpleTimingPort
{
protected:
PciDev *device;
PciDevice *device;
virtual Tick recvAtomic(PacketPtr pkt);
@@ -76,7 +76,7 @@ class PciDev : public DmaDevice
Addr configAddr;
public:
PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
PciConfigPort(PciDevice *dev, int busid, int devid, int funcid,
Platform *p);
};
@@ -198,7 +198,7 @@ class PciDev : public DmaDevice
* config file object PCIConfigData and registers the device with
* a PciConfigAll object.
*/
PciDev(const Params *params);
PciDevice(const Params *params);
virtual void init();

12
src/dev/sinic.cc
View File

@@ -1263,8 +1263,8 @@ Device::drainResume()
void
Base::serialize(std::ostream &os)
{
// Serialize the PciDev base class
PciDev::serialize(os);
// Serialize the PciDevice base class
PciDevice::serialize(os);
SERIALIZE_SCALAR(rxEnable);
SERIALIZE_SCALAR(txEnable);
@@ -1284,8 +1284,8 @@ Base::serialize(std::ostream &os)
void
Base::unserialize(Checkpoint *cp, const std::string &section)
{
// Unserialize the PciDev base class
PciDev::unserialize(cp, section);
// Unserialize the PciDevice base class
PciDevice::unserialize(cp, section);
UNSERIALIZE_SCALAR(rxEnable);
UNSERIALIZE_SCALAR(txEnable);
@@ -1309,7 +1309,7 @@ Device::serialize(std::ostream &os)
{
int count;
// Serialize the PciDev base class
// Serialize the PciDevice base class
Base::serialize(os);
if (rxState == rxCopy)
@@ -1422,7 +1422,7 @@ Device::serialize(std::ostream &os)
void
Device::unserialize(Checkpoint *cp, const std::string &section)
{
// Unserialize the PciDev base class
// Unserialize the PciDevice base class
Base::unserialize(cp, section);
/*

2
src/dev/x86/SConscript
View File

@@ -67,4 +67,4 @@ if env['TARGET_ISA'] == 'x86':
SimObject('X86IntPin.py')
Source('intdev.cc')
DebugFlag('IntDev')
DebugFlag('IntDevice')

6
src/dev/x86/i82094aa.cc
View File

@@ -39,7 +39,7 @@
#include "sim/system.hh"
X86ISA::I82094AA::I82094AA(Params *p)
: BasicPioDevice(p), IntDev(this, p->int_latency),
: BasicPioDevice(p), IntDevice(this, p->int_latency),
extIntPic(p->external_int_pic), lowestPriorityOffset(0)
{
// This assumes there's only one I/O APIC in the system and since the apic
@@ -65,10 +65,10 @@ X86ISA::I82094AA::init()
{
// The io apic must register its address ranges on both its pio port
// via the piodevice init() function and its int port that it inherited
// from IntDev. Note IntDev is not a SimObject itself.
// from IntDevice. Note IntDevice is not a SimObject itself.
BasicPioDevice::init();
IntDev::init();
IntDevice::init();
}
BaseMasterPort &

2
src/dev/x86/i82094aa.hh
View File

@@ -44,7 +44,7 @@ namespace X86ISA
class I8259;
class Interrupts;
class I82094AA : public BasicPioDevice, public IntDev
class I82094AA : public BasicPioDevice, public IntDevice
{
public:
BitUnion64(RedirTableEntry)

2
src/dev/x86/i8259.cc
View File

@@ -35,7 +35,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDevice(this),
latency(p->pio_latency), output(p->output),
mode(p->mode), slave(p->slave),
IRR(0), ISR(0), IMR(0),

2
src/dev/x86/i8259.hh
View File

@@ -39,7 +39,7 @@
namespace X86ISA
{
class I8259 : public BasicPioDevice, public IntDev
class I8259 : public BasicPioDevice, public IntDevice
{
protected:
static const int NumLines = 8;

4
src/dev/x86/intdev.cc
View File

@@ -43,7 +43,7 @@
#include "dev/x86/intdev.hh"
void
X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics,
X86ISA::IntDevice::IntMasterPort::sendMessage(ApicList apics,
TriggerIntMessage message,
bool timing)
{
@@ -66,7 +66,7 @@ X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics,
}
void
X86ISA::IntDev::init()
X86ISA::IntDevice::init()
{
if (!intMasterPort.isConnected()) {
panic("Int port not connected to anything!");

18
src/dev/x86/intdev.hh
View File

@@ -60,16 +60,16 @@ namespace X86ISA {
typedef std::list<int> ApicList;
class IntDev
class IntDevice
{
protected:
class IntSlavePort : public MessageSlavePort
{
IntDev * device;
IntDevice * device;
public:
IntSlavePort(const std::string& _name, MemObject* _parent,
IntDev* dev) :
IntDevice* dev) :
MessageSlavePort(_name, _parent), device(dev)
{
}
@@ -89,11 +89,11 @@ class IntDev
class IntMasterPort : public MessageMasterPort
{
IntDev* device;
IntDevice* device;
Tick latency;
public:
IntMasterPort(const std::string& _name, MemObject* _parent,
IntDev* dev, Tick _latency) :
IntDevice* dev, Tick _latency) :
MessageMasterPort(_name, _parent), device(dev), latency(_latency)
{
}
@@ -112,12 +112,12 @@ class IntDev
IntMasterPort intMasterPort;
public:
IntDev(MemObject * parent, Tick latency = 0) :
IntDevice(MemObject * parent, Tick latency = 0) :
intMasterPort(parent->name() + ".int_master", parent, this, latency)
{
}
virtual ~IntDev()
virtual ~IntDevice()
{}
virtual void init();
@@ -163,7 +163,7 @@ class IntDev
class IntSinkPin : public SimObject
{
public:
IntDev * device;
IntDevice * device;
int number;
typedef X86IntSinkPinParams Params;
@@ -175,7 +175,7 @@ class IntSinkPin : public SimObject
}
IntSinkPin(Params *p) : SimObject(p),
device(dynamic_cast<IntDev *>(p->device)), number(p->number)
device(dynamic_cast<IntDevice *>(p->device)), number(p->number)
{
assert(device);
}