From 502ad1e6757116867e0e0529c0c080320a2b440b Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Thu, 11 Jul 2013 21:56:50 -0500 Subject: [PATCH] dev: consistently end device classes in 'Device' PciDev and IntDev stuck out as the only device classes that ended in 'Dev' rather than 'Device'. This patch takes care of that inconsistency. Note that you may need to delete pre-existing files matching build/*/python/m5/internal/param_* as scons does not pick up indirect dependencies on imported python modules when generating params, and the PciDev -> PciDevice rename takes place in a file (dev/Device.py) that gets imported quite a bit. Committed by: Nilay Vaish --- src/arch/x86/interrupts.cc | 31 ++++++++++++++++--------------- src/arch/x86/interrupts.hh | 4 ++-- src/dev/Pci.py | 2 +- src/dev/copy_engine.cc | 8 ++++---- src/dev/copy_engine.hh | 2 +- src/dev/etherdevice.hh | 4 ++-- src/dev/i8254xGBe.cc | 8 ++++---- src/dev/ide_ctrl.cc | 16 ++++++++-------- src/dev/ide_ctrl.hh | 2 +- src/dev/ns_gige.cc | 10 +++++----- src/dev/pciconfigall.hh | 10 +++++----- src/dev/pcidev.cc | 22 +++++++++++----------- src/dev/pcidev.hh | 8 ++++---- src/dev/sinic.cc | 12 ++++++------ src/dev/x86/SConscript | 2 +- src/dev/x86/i82094aa.cc | 6 +++--- src/dev/x86/i82094aa.hh | 2 +- src/dev/x86/i8259.cc | 2 +- src/dev/x86/i8259.hh | 2 +- src/dev/x86/intdev.cc | 4 ++-- src/dev/x86/intdev.hh | 18 +++++++++--------- 21 files changed, 88 insertions(+), 87 deletions(-) diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index ae01f921f8..eba4b0010f 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -311,12 +311,13 @@ void X86ISA::Interrupts::init() { // - // The local apic must register its address ranges on both its pio port - // via the basicpiodevice(piodevice) init() function and its int port - // that it inherited from IntDev. Note IntDev is not a SimObject itself. + // The local apic must register its address ranges on both its pio + // port via the basicpiodevice(piodevice) init() function and its + // int port that it inherited from IntDevice. Note IntDevice is + // not a SimObject itself. // BasicPioDevice::init(); - IntDev::init(); + IntDevice::init(); // the slave port has a range so inform the connected master intSlavePort.sendRangeChange(); @@ -606,17 +607,17 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) } -X86ISA::Interrupts::Interrupts(Params * p) : - BasicPioDevice(p), IntDev(this, p->int_latency), - apicTimerEvent(this), - pendingSmi(false), smiVector(0), - pendingNmi(false), nmiVector(0), - pendingExtInt(false), extIntVector(0), - pendingInit(false), initVector(0), - pendingStartup(false), startupVector(0), - startedUp(false), pendingUnmaskableInt(false), - pendingIPIs(0), cpu(NULL), - intSlavePort(name() + ".int_slave", this, this) +X86ISA::Interrupts::Interrupts(Params * p) + : BasicPioDevice(p), IntDevice(this, p->int_latency), + apicTimerEvent(this), + pendingSmi(false), smiVector(0), + pendingNmi(false), nmiVector(0), + pendingExtInt(false), extIntVector(0), + pendingInit(false), initVector(0), + pendingStartup(false), startupVector(0), + startedUp(false), pendingUnmaskableInt(false), + pendingIPIs(0), cpu(NULL), + intSlavePort(name() + ".int_slave", this, this) { pioSize = PageBytes; memset(regs, 0, sizeof(regs)); diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 959a615139..da0d767fdc 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -72,7 +72,7 @@ namespace X86ISA { ApicRegIndex decodeAddr(Addr paddr); -class Interrupts : public BasicPioDevice, IntDev +class Interrupts : public BasicPioDevice, IntDevice { protected: // Storage for the APIC registers @@ -215,7 +215,7 @@ class Interrupts : public BasicPioDevice, IntDev void init(); /* - * Functions to interact with the interrupt port from IntDev. + * Functions to interact with the interrupt port from IntDevice. */ Tick read(PacketPtr pkt); Tick write(PacketPtr pkt); diff --git a/src/dev/Pci.py b/src/dev/Pci.py index a63c329a44..fa3fc854e0 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -44,7 +44,7 @@ class PciConfigAll(BasicPioDevice): class PciDevice(DmaDevice): type = 'PciDevice' - cxx_class = 'PciDev' + cxx_class = 'PciDevice' cxx_header = "dev/pcidev.hh" abstract = True platform = Param.Platform(Parent.any, "Platform this device is part of.") diff --git a/src/dev/copy_engine.cc b/src/dev/copy_engine.cc index d6162b6899..e4cd90c1c3 100644 --- a/src/dev/copy_engine.cc +++ b/src/dev/copy_engine.cc @@ -60,7 +60,7 @@ using namespace CopyEngineReg; CopyEngine::CopyEngine(const Params *p) - : PciDev(p) + : PciDevice(p) { // All Reg regs are initialized to 0 by default regs.chanCount = p->ChanCnt; @@ -115,7 +115,7 @@ CopyEngine::getMasterPort(const std::string &if_name, PortID idx) { if (if_name != "dma") { // pass it along to our super class - return PciDev::getMasterPort(if_name, idx); + return PciDevice::getMasterPort(if_name, idx); } else { if (idx >= static_cast(chan.size())) { panic("CopyEngine::getMasterPort: unknown index %d\n", idx); @@ -680,7 +680,7 @@ CopyEngine::drain(DrainManager *dm) void CopyEngine::serialize(std::ostream &os) { - PciDev::serialize(os); + PciDevice::serialize(os); regs.serialize(os); for (int x =0; x < chan.size(); x++) { nameOut(os, csprintf("%s.channel%d", name(), x)); @@ -691,7 +691,7 @@ CopyEngine::serialize(std::ostream &os) void CopyEngine::unserialize(Checkpoint *cp, const std::string §ion) { - PciDev::unserialize(cp, section); + PciDevice::unserialize(cp, section); regs.unserialize(cp, section); for (int x = 0; x < chan.size(); x++) chan[x]->unserialize(cp, csprintf("%s.channel%d", section, x)); diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh index c4b07c79d1..1186d0b1dd 100644 --- a/src/dev/copy_engine.hh +++ b/src/dev/copy_engine.hh @@ -58,7 +58,7 @@ #include "sim/drain.hh" #include "sim/eventq.hh" -class CopyEngine : public PciDev +class CopyEngine : public PciDevice { class CopyEngineChannel : public Drainable { diff --git a/src/dev/etherdevice.hh b/src/dev/etherdevice.hh index 81e5535b05..ace600a4e1 100644 --- a/src/dev/etherdevice.hh +++ b/src/dev/etherdevice.hh @@ -48,12 +48,12 @@ class EtherInt; * The base EtherObject class, allows for an accesor function to a * simobj that returns the Port. */ -class EtherDevice : public PciDev +class EtherDevice : public PciDevice { public: typedef EtherDeviceParams Params; EtherDevice(const Params *params) - : PciDev(params) + : PciDevice(params) {} const Params * diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index ee24b3922c..e65baba892 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -131,7 +131,7 @@ void IGbE::init() { cpa = CPA::cpa(); - PciDev::init(); + PciDevice::init(); } EtherInt* @@ -151,7 +151,7 @@ IGbE::writeConfig(PacketPtr pkt) { int offset = pkt->getAddr() & PCI_CONFIG_SIZE; if (offset < PCI_DEVICE_SPECIFIC) - PciDev::writeConfig(pkt); + PciDevice::writeConfig(pkt); else panic("Device specific PCI config space not implemented.\n"); @@ -2453,7 +2453,7 @@ IGbE::ethTxDone() void IGbE::serialize(std::ostream &os) { - PciDev::serialize(os); + PciDevice::serialize(os); regs.serialize(os); SERIALIZE_SCALAR(eeOpBits); @@ -2507,7 +2507,7 @@ IGbE::serialize(std::ostream &os) void IGbE::unserialize(Checkpoint *cp, const std::string §ion) { - PciDev::unserialize(cp, section); + PciDevice::unserialize(cp, section); regs.unserialize(cp, section); UNSERIALIZE_SCALAR(eeOpBits); diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc index f33d603af1..df02bf5f56 100644 --- a/src/dev/ide_ctrl.cc +++ b/src/dev/ide_ctrl.cc @@ -80,7 +80,7 @@ IdeController::Channel::~Channel() } IdeController::IdeController(Params *p) - : PciDev(p), primary(name() + ".primary", BARSize[0], BARSize[1]), + : PciDevice(p), primary(name() + ".primary", BARSize[0], BARSize[1]), secondary(name() + ".secondary", BARSize[2], BARSize[3]), bmiAddr(0), bmiSize(BARSize[4]), primaryTiming(htole(timeRegWithDecodeEn)), @@ -132,7 +132,7 @@ void IdeController::intrPost() { primary.bmiRegs.status.intStatus = 1; - PciDev::intrPost(); + PciDevice::intrPost(); } void @@ -157,7 +157,7 @@ IdeController::readConfig(PacketPtr pkt) { int offset = pkt->getAddr() & PCI_CONFIG_SIZE; if (offset < PCI_DEVICE_SPECIFIC) { - return PciDev::readConfig(pkt); + return PciDevice::readConfig(pkt); } pkt->allocate(); @@ -232,7 +232,7 @@ IdeController::writeConfig(PacketPtr pkt) { int offset = pkt->getAddr() & PCI_CONFIG_SIZE; if (offset < PCI_DEVICE_SPECIFIC) { - PciDev::writeConfig(pkt); + PciDevice::writeConfig(pkt); } else { switch (pkt->getSize()) { case sizeof(uint8_t): @@ -523,8 +523,8 @@ IdeController::write(PacketPtr pkt) void IdeController::serialize(std::ostream &os) { - // Serialize the PciDev base class - PciDev::serialize(os); + // Serialize the PciDevice base class + PciDevice::serialize(os); // Serialize channels primary.serialize("primary", os); @@ -565,8 +565,8 @@ IdeController::Channel::serialize(const std::string &base, std::ostream &os) void IdeController::unserialize(Checkpoint *cp, const std::string §ion) { - // Unserialize the PciDev base class - PciDev::unserialize(cp, section); + // Unserialize the PciDevice base class + PciDevice::unserialize(cp, section); // Unserialize channels primary.unserialize("primary", cp, section); diff --git a/src/dev/ide_ctrl.hh b/src/dev/ide_ctrl.hh index 93291ad663..414e310873 100644 --- a/src/dev/ide_ctrl.hh +++ b/src/dev/ide_ctrl.hh @@ -49,7 +49,7 @@ class IdeDisk; * Device model for an Intel PIIX4 IDE controller */ -class IdeController : public PciDev +class IdeController : public PciDevice { private: // Bus master IDE status register bit fields diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 9269f79356..67f8e0345a 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -146,7 +146,7 @@ NSGigE::writeConfig(PacketPtr pkt) { int offset = pkt->getAddr() & PCI_CONFIG_SIZE; if (offset < PCI_DEVICE_SPECIFIC) - PciDev::writeConfig(pkt); + PciDevice::writeConfig(pkt); else panic("Device specific PCI config space not implemented!\n"); @@ -2126,8 +2126,8 @@ NSGigE::drainResume() void NSGigE::serialize(ostream &os) { - // Serialize the PciDev base class - PciDev::serialize(os); + // Serialize the PciDevice base class + PciDevice::serialize(os); /* * Finalize any DMA events now. @@ -2298,8 +2298,8 @@ NSGigE::serialize(ostream &os) void NSGigE::unserialize(Checkpoint *cp, const std::string §ion) { - // Unserialize the PciDev base class - PciDev::unserialize(cp, section); + // Unserialize the PciDevice base class + PciDevice::unserialize(cp, section); UNSERIALIZE_SCALAR(regs.command); UNSERIALIZE_SCALAR(regs.config); diff --git a/src/dev/pciconfigall.hh b/src/dev/pciconfigall.hh index 615b3578f8..c9a63d2c5d 100644 --- a/src/dev/pciconfigall.hh +++ b/src/dev/pciconfigall.hh @@ -45,7 +45,7 @@ * PCI Config Space * All of PCI config space needs to return -1 on Tsunami, except * the devices that exist. This device maps the entire bus config - * space and passes the requests on to TsunamiPCIDev devices as + * space and passes the requests on to TsunamiPCIDevice devices as * appropriate. */ class PciConfigAll : public BasicPioDevice @@ -62,8 +62,8 @@ class PciConfigAll : public BasicPioDevice /** * Read something in PCI config space. If the device does not exist - * -1 is returned, if the device does exist its PciDev::ReadConfig (or the - * virtual function that overrides) it is called. + * -1 is returned, if the device does exist its PciDevice::ReadConfig + * (or the virtual function that overrides) it is called. * @param pkt Contains information about the read operation * @return Amount of time to do the read */ @@ -71,8 +71,8 @@ class PciConfigAll : public BasicPioDevice /** * Write to PCI config spcae. If the device does not exit the simulator - * panics. If it does it is passed on the PciDev::WriteConfig (or the virtual - * function that overrides it). + * panics. If it does it is passed on the PciDevice::WriteConfig (or + * the virtual function that overrides it). * @param pkt Contains information about the write operation * @return Amount of time to do the read */ diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index af78f51801..3ca807d066 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -53,7 +53,7 @@ #include "sim/core.hh" -PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid, +PciDevice::PciConfigPort::PciConfigPort(PciDevice *dev, int busid, int devid, int funcid, Platform *p) : SimpleTimingPort(dev->name() + "-pciconf", dev), device(dev), platform(p), busId(busid), deviceId(devid), functionId(funcid) @@ -63,7 +63,7 @@ PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid, Tick -PciDev::PciConfigPort::recvAtomic(PacketPtr pkt) +PciDevice::PciConfigPort::recvAtomic(PacketPtr pkt) { assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr + PCI_CONFIG_SIZE); @@ -73,7 +73,7 @@ PciDev::PciConfigPort::recvAtomic(PacketPtr pkt) } AddrRangeList -PciDev::PciConfigPort::getAddrRanges() const +PciDevice::PciConfigPort::getAddrRanges() const { AddrRangeList ranges; if (configAddr != ULL(-1)) @@ -82,7 +82,7 @@ PciDev::PciConfigPort::getAddrRanges() const } -PciDev::PciDev(const Params *p) +PciDevice::PciDevice(const Params *p) : DmaDevice(p), platform(p->platform), pioDelay(p->pio_latency), configDelay(p->config_latency), configPort(this, params()->pci_bus, params()->pci_dev, @@ -150,7 +150,7 @@ PciDev::PciDev(const Params *p) } void -PciDev::init() +PciDevice::init() { if (!configPort.isConnected()) panic("PCI config port on %s not connected to anything!\n", name()); @@ -159,7 +159,7 @@ PciDev::init() } unsigned int -PciDev::drain(DrainManager *dm) +PciDevice::drain(DrainManager *dm) { unsigned int count; count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm); @@ -171,7 +171,7 @@ PciDev::drain(DrainManager *dm) } Tick -PciDev::readConfig(PacketPtr pkt) +PciDevice::readConfig(PacketPtr pkt) { int offset = pkt->getAddr() & PCI_CONFIG_SIZE; if (offset >= PCI_DEVICE_SPECIFIC) @@ -210,7 +210,7 @@ PciDev::readConfig(PacketPtr pkt) } AddrRangeList -PciDev::getAddrRanges() const +PciDevice::getAddrRanges() const { AddrRangeList ranges; int x = 0; @@ -221,7 +221,7 @@ PciDev::getAddrRanges() const } Tick -PciDev::writeConfig(PacketPtr pkt) +PciDevice::writeConfig(PacketPtr pkt) { int offset = pkt->getAddr() & PCI_CONFIG_SIZE; if (offset >= PCI_DEVICE_SPECIFIC) @@ -343,7 +343,7 @@ PciDev::writeConfig(PacketPtr pkt) } void -PciDev::serialize(std::ostream &os) +PciDevice::serialize(std::ostream &os) { SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0])); SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0])); @@ -351,7 +351,7 @@ PciDev::serialize(std::ostream &os) } void -PciDev::unserialize(Checkpoint *cp, const std::string §ion) +PciDevice::unserialize(Checkpoint *cp, const std::string §ion) { UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0])); UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0])); diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index df468d4c62..d4820c0eef 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -56,12 +56,12 @@ /** * PCI device, base implementation is only config space. */ -class PciDev : public DmaDevice +class PciDevice : public DmaDevice { class PciConfigPort : public SimpleTimingPort { protected: - PciDev *device; + PciDevice *device; virtual Tick recvAtomic(PacketPtr pkt); @@ -76,7 +76,7 @@ class PciDev : public DmaDevice Addr configAddr; public: - PciConfigPort(PciDev *dev, int busid, int devid, int funcid, + PciConfigPort(PciDevice *dev, int busid, int devid, int funcid, Platform *p); }; @@ -198,7 +198,7 @@ class PciDev : public DmaDevice * config file object PCIConfigData and registers the device with * a PciConfigAll object. */ - PciDev(const Params *params); + PciDevice(const Params *params); virtual void init(); diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 8cb7aada7c..c2d5fb49d0 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1263,8 +1263,8 @@ Device::drainResume() void Base::serialize(std::ostream &os) { - // Serialize the PciDev base class - PciDev::serialize(os); + // Serialize the PciDevice base class + PciDevice::serialize(os); SERIALIZE_SCALAR(rxEnable); SERIALIZE_SCALAR(txEnable); @@ -1284,8 +1284,8 @@ Base::serialize(std::ostream &os) void Base::unserialize(Checkpoint *cp, const std::string §ion) { - // Unserialize the PciDev base class - PciDev::unserialize(cp, section); + // Unserialize the PciDevice base class + PciDevice::unserialize(cp, section); UNSERIALIZE_SCALAR(rxEnable); UNSERIALIZE_SCALAR(txEnable); @@ -1309,7 +1309,7 @@ Device::serialize(std::ostream &os) { int count; - // Serialize the PciDev base class + // Serialize the PciDevice base class Base::serialize(os); if (rxState == rxCopy) @@ -1422,7 +1422,7 @@ Device::serialize(std::ostream &os) void Device::unserialize(Checkpoint *cp, const std::string §ion) { - // Unserialize the PciDev base class + // Unserialize the PciDevice base class Base::unserialize(cp, section); /* diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript index 038e4824b8..331f0a229c 100644 --- a/src/dev/x86/SConscript +++ b/src/dev/x86/SConscript @@ -67,4 +67,4 @@ if env['TARGET_ISA'] == 'x86': SimObject('X86IntPin.py') Source('intdev.cc') - DebugFlag('IntDev') + DebugFlag('IntDevice') diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc index 1d3defa121..f547d7c1b1 100644 --- a/src/dev/x86/i82094aa.cc +++ b/src/dev/x86/i82094aa.cc @@ -39,7 +39,7 @@ #include "sim/system.hh" X86ISA::I82094AA::I82094AA(Params *p) - : BasicPioDevice(p), IntDev(this, p->int_latency), + : BasicPioDevice(p), IntDevice(this, p->int_latency), extIntPic(p->external_int_pic), lowestPriorityOffset(0) { // This assumes there's only one I/O APIC in the system and since the apic @@ -65,10 +65,10 @@ X86ISA::I82094AA::init() { // The io apic must register its address ranges on both its pio port // via the piodevice init() function and its int port that it inherited - // from IntDev. Note IntDev is not a SimObject itself. + // from IntDevice. Note IntDevice is not a SimObject itself. BasicPioDevice::init(); - IntDev::init(); + IntDevice::init(); } BaseMasterPort & diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh index a8d79fde18..4fe927ae41 100644 --- a/src/dev/x86/i82094aa.hh +++ b/src/dev/x86/i82094aa.hh @@ -44,7 +44,7 @@ namespace X86ISA class I8259; class Interrupts; -class I82094AA : public BasicPioDevice, public IntDev +class I82094AA : public BasicPioDevice, public IntDevice { public: BitUnion64(RedirTableEntry) diff --git a/src/dev/x86/i8259.cc b/src/dev/x86/i8259.cc index 4e8c101818..fa54ad5d7c 100644 --- a/src/dev/x86/i8259.cc +++ b/src/dev/x86/i8259.cc @@ -35,7 +35,7 @@ #include "mem/packet.hh" #include "mem/packet_access.hh" -X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this), +X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDevice(this), latency(p->pio_latency), output(p->output), mode(p->mode), slave(p->slave), IRR(0), ISR(0), IMR(0), diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh index eee5ec171d..2d6080cc3a 100644 --- a/src/dev/x86/i8259.hh +++ b/src/dev/x86/i8259.hh @@ -39,7 +39,7 @@ namespace X86ISA { -class I8259 : public BasicPioDevice, public IntDev +class I8259 : public BasicPioDevice, public IntDevice { protected: static const int NumLines = 8; diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc index 3f8e49ce1d..8830733023 100644 --- a/src/dev/x86/intdev.cc +++ b/src/dev/x86/intdev.cc @@ -43,7 +43,7 @@ #include "dev/x86/intdev.hh" void -X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics, +X86ISA::IntDevice::IntMasterPort::sendMessage(ApicList apics, TriggerIntMessage message, bool timing) { @@ -66,7 +66,7 @@ X86ISA::IntDev::IntMasterPort::sendMessage(ApicList apics, } void -X86ISA::IntDev::init() +X86ISA::IntDevice::init() { if (!intMasterPort.isConnected()) { panic("Int port not connected to anything!"); diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh index 99c361bae7..078ea2b6fc 100644 --- a/src/dev/x86/intdev.hh +++ b/src/dev/x86/intdev.hh @@ -60,16 +60,16 @@ namespace X86ISA { typedef std::list ApicList; -class IntDev +class IntDevice { protected: class IntSlavePort : public MessageSlavePort { - IntDev * device; + IntDevice * device; public: IntSlavePort(const std::string& _name, MemObject* _parent, - IntDev* dev) : + IntDevice* dev) : MessageSlavePort(_name, _parent), device(dev) { } @@ -89,11 +89,11 @@ class IntDev class IntMasterPort : public MessageMasterPort { - IntDev* device; + IntDevice* device; Tick latency; public: IntMasterPort(const std::string& _name, MemObject* _parent, - IntDev* dev, Tick _latency) : + IntDevice* dev, Tick _latency) : MessageMasterPort(_name, _parent), device(dev), latency(_latency) { } @@ -112,12 +112,12 @@ class IntDev IntMasterPort intMasterPort; public: - IntDev(MemObject * parent, Tick latency = 0) : + IntDevice(MemObject * parent, Tick latency = 0) : intMasterPort(parent->name() + ".int_master", parent, this, latency) { } - virtual ~IntDev() + virtual ~IntDevice() {} virtual void init(); @@ -163,7 +163,7 @@ class IntDev class IntSinkPin : public SimObject { public: - IntDev * device; + IntDevice * device; int number; typedef X86IntSinkPinParams Params; @@ -175,7 +175,7 @@ class IntSinkPin : public SimObject } IntSinkPin(Params *p) : SimObject(p), - device(dynamic_cast(p->device)), number(p->number) + device(dynamic_cast(p->device)), number(p->number) { assert(device); }