Éder F. Zulian
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ea23659579
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improvements
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2017-12-07 17:56:56 +01:00 |
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Éder F. Zulian
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1ebef99bf1
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Readme improved
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2017-12-07 12:59:02 +01:00 |
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Éder F. Zulian
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5b4d1bebfd
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Improvements.
Scripts to install dependencies.
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2017-12-07 12:53:21 +01:00 |
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Éder F. Zulian
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3f7bd04b56
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readme updated
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2017-12-06 15:22:03 +01:00 |
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Éder F. Zulian
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2f7328afc4
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Readme file updated
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2017-12-06 15:20:47 +01:00 |
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Éder F. Zulian
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820cb70494
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Basic git configs are required before cloning
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2017-12-06 15:08:24 +01:00 |
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Éder F. Zulian
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b0ce963fa3
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Utility to get systemC library v.2.3.1 installed
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2017-12-06 12:10:19 +01:00 |
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Éder F. Zulian
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22127bcace
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Names fixed
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2017-11-07 16:04:16 +01:00 |
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Éder F. Zulian
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58f44d319f
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Some links to files fixed
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2017-11-07 16:01:27 +01:00 |
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Éder F. Zulian
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003cb582a2
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Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
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2017-11-07 15:46:25 +01:00 |
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Éder F. Zulian
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a121f1de9f
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Link to dramsylva folder fixed
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2017-11-07 15:45:57 +01:00 |
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fzeder
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c2bbcf8ff3
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Merge pull request #184 from anaclara/master
DRAMSylva uses the same latency range for all plots
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2017-11-06 19:48:20 +01:00 |
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Ana Mativi
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ddeeeeb0e8
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Updating metric name and using 50 bins as default
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2017-11-06 18:26:36 +01:00 |
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Ana Mativi
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4d9ec186dc
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Improvements for DRAMSylva latency plot
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2017-10-26 18:10:49 +02:00 |
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Ana Mativi
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c2560e5c7d
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DRAMSylva uses the same latency range for all plots
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2017-10-25 13:40:46 +02:00 |
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Éder F. Zulian
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60877d778b
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Plot generation improved
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2017-10-06 19:01:00 +02:00 |
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Ana Mativi
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4f8093061e
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Adding variable git_repo to DRAMSylva
This implementation was made by Ana Mativi <anaclara@rhrk.uni-kl.de> and
removed by mistake in 14c4a041bd.
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2017-10-06 15:35:24 +02:00 |
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Ana Mativi
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381761f0fa
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Adding number of refreshes to metrics
This new metric was implemented by Ana Mativi <anaclara@rhrk.uni-kl.de> and
then removed by mistake in 14c4a041bd.
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2017-10-06 15:21:05 +02:00 |
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Matthias Jung
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427b76663a
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Added also clock cycle to dragging in Analyzer
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2017-10-04 09:48:10 -04:00 |
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Éder F. Zulian
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03bb8763bf
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Sim. file fixed
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2017-10-04 14:25:13 +02:00 |
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Éder F. Zulian
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91761805f0
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Example config files
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2017-10-04 11:21:01 +02:00 |
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Éder F. Zulian
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5c1a113650
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Submodules are back!
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2017-10-04 11:07:20 +02:00 |
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Matthias Jung
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14c4a041bd
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Reorganized such that build dependencies wont fail
Also some LPDDR4 starting was conducted
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2017-10-03 18:20:13 -04:00 |
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fzeder
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0d64a49521
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Merge pull request #183 from anaclara/master
Adding number of refreshes to metrics
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2017-09-28 18:42:02 +02:00 |
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Ana Mativi
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d0d7cd0628
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Adding number of refreshes to metrics
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2017-09-28 17:39:08 +02:00 |
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fzeder
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02fdf9a22b
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Merge pull request #182 from anaclara/master
Adding variable git_repo to DRAMSylva
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2017-09-19 15:17:17 +02:00 |
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Ana Mativi
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6a071bbc6d
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Adding variable git_repo to DRAMSylva
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2017-09-19 15:02:59 +02:00 |
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Éder F. Zulian
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b007245515
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SimulationID --> simulationid
Comments added.
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2017-09-08 10:45:29 +02:00 |
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Éder F. Zulian
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a610b54349
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Simulation ID added to simulation files
New example file ddr3-example2.xml which has two trace players.
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2017-09-07 19:25:54 +02:00 |
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Matthias Jung
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959e1ddccc
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Added RW to HOG
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2017-08-20 20:21:57 +02:00 |
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Éder F. Zulian
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8782b3dcd9
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dramSylva --> DRAMSylva
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2017-08-18 16:29:54 +02:00 |
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Matthias Jung
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83fa1a301a
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Merge pull request #178 from anaclara/master
Adding Postpone Ref related configurations
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2017-08-18 16:14:35 +02:00 |
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Ana Mativi
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5c2cee5999
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Adding Postpone Ref related configurations
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2017-08-18 15:58:14 +02:00 |
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Matthias Jung
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f50effbf06
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Updated conf. examples for gem5 to new version
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2017-08-18 15:10:12 +02:00 |
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Éder F. Zulian
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69a83536e2
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dramSylva now generates a CSV with metrics
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2017-08-17 16:03:52 +02:00 |
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Éder F. Zulian
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041a9f310a
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File renamed
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2017-08-17 11:45:13 +02:00 |
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fzeder
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cfbbecdaaf
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Merge pull request #177 from anaclara/master
Adding metrics to dramSylva
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2017-08-15 19:08:54 +02:00 |
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Ana Mativi
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ec941b4301
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Try to clone first with SSH, using HTTPS in case of failure. README updated
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2017-08-15 18:29:04 +02:00 |
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Ana Mativi
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1ead5c0c32
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Adding metrics to dramSylva
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2017-08-15 15:56:35 +02:00 |
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Éder F. Zulian
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5b16c7caf5
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Plot generation feature added to dramSylva
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2017-08-15 12:43:33 +02:00 |
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Éder F. Zulian
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ba592e28e6
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Add comments to dramSylva
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2017-08-15 11:51:16 +02:00 |
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Éder F. Zulian
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f48c781c1f
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dramSylva gets num. of cores from proc filesystem
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2017-08-14 10:41:17 +02:00 |
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Éder F. Zulian
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8be2ff4fd9
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Simulation log collector script added to repo
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2017-08-11 13:08:52 +02:00 |
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Éder F. Zulian
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ef741cf744
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Comments added to the code
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2017-08-08 14:37:08 +02:00 |
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fzeder
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c1e9949850
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Merge pull request #176 from anaclara/master
Postpone Refresh feature is only available for DDR3 currently
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2017-08-08 13:58:10 +02:00 |
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Ana Mativi
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76d985d3f5
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Added fatal error if ControllerCoreEnableRefPostpone is enabled and memSpec is not DDR3
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2017-08-08 13:26:20 +02:00 |
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Ana Mativi
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466fbab9ba
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loadMemSpec executes before loadMCConfig
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2017-08-08 13:25:36 +02:00 |
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Ana Mativi
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e2e389f075
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Adding myself as an author for RefreshManager
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2017-08-08 13:21:02 +02:00 |
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fzeder
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462d4f5ebc
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Merge pull request #173 from anaclara/master
Postpone Refresh Implementation.
This initial version supports DDR3 only.
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2017-08-08 10:13:42 +02:00 |
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Ana Mativi
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a4bd237418
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Patch for Postpone Ref Implementation
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2017-08-07 18:12:16 +02:00 |
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