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Sim. file fixed

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This commit is contained in:
Éder F. Zulian
2017-10-04 14:25:13 +02:00
parent 91761805f0
commit 03bb8763bf
3 changed files with 6 additions and 40 deletions
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13
DRAMSys/library/resources/simulations/ddr3-example.xml
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@@ -8,7 +8,7 @@
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_rbc.xml"></addressmapping>
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
@@ -20,15 +20,6 @@
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="530">ip1.stl</device>
<device clkMhz="530">ip2.stl</device>
<device clkMhz="530">ip3.stl</device>
<device clkMhz="530">ip4.stl</device>
<device clkMhz="530">ip5.stl</device>
<device clkMhz="530">ip6.stl</device>
<device clkMhz="530">ip7.stl</device>
<device clkMhz="530">ip8.stl</device>
<device clkMhz="530">ip9.stl</device>
<device clkMhz="530">ip10.stl</device>
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

7
DRAMSys/library/resources/simulations/ddr3-example2.xml
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@@ -17,9 +17,10 @@
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
Two memory bus master devices, one running at 300 MHz and the
other at 400 MHz.
-->
<device clkMhz="200">ddr3_example.stl</device>
<device clkMhz="300">ddr3_example.stl</device>
<device clkMhz="400">ddr3_example.stl</device>
</tracesetup>
</simulation>

26
DRAMSys/library/resources/simulations/ddr3-example3.xml
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@@ -1,26 +0,0 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example3"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
Two memory bus master devices, one running at 300 MHz and the
other at 400 MHz.
-->
<device clkMhz="300">ddr3_example.stl</device>
<device clkMhz="400">ddr3_example.stl</device>
</tracesetup>
</simulation>