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Updated conf. examples for gem5 to new version

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This commit is contained in:
Matthias Jung
2017-08-18 15:10:12 +02:00
parent 69a83536e2
commit f50effbf06
3 changed files with 1527 additions and 2 deletions
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4
DRAMSys/gem5/configs/dualElasticTraceReplay.ini
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@@ -97,6 +97,7 @@ switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu0.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
@@ -279,6 +280,7 @@ id_mmfr3=34611729
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu0.istage2_mmu]
type=ArmStage2MMU
@@ -380,6 +382,7 @@ switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu1.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
@@ -562,6 +565,7 @@ id_mmfr3=34611729
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu1.istage2_mmu]
type=ArmStage2MMU

1519
DRAMSys/gem5/configs/nvdimmp.ini Normal file
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File diff suppressed because it is too large Load Diff

6
DRAMSys/gem5/configs/singleElasticTraceReplay.ini
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@@ -59,7 +59,7 @@ children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.clk_domain
cpu_id=0
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz
dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
@@ -71,7 +71,7 @@ eventq_index=0
freqMultiplier=1.0
function_trace=false
function_trace_start=0
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz
instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.inst.gz
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
@@ -97,6 +97,7 @@ switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
@@ -279,6 +280,7 @@ id_mmfr3=34611729
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU