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Author SHA1 Message Date
Felipe Salerno Prado
cd9760bf80 Updates 2016-06-01 14:58:31 +02:00
Felipe Salerno Prado
c61a41daf5 Merge remote branch 'upstream/master' 2016-06-01 14:34:27 +02:00
sprado
655ef76a6c Tests update 2016-06-01 13:04:58 +02:00
Éder F. Zulian
417b454726 Simple test updated 2016-05-31 18:01:02 +02:00
fzeder
a83e54c3a6 Merge pull request #83 from Flauer/Bandwidth_Edit 
Bandwidth edit
 2016-05-31 17:45:53 +02:00
Felipe Salerno Prado
1df8fef4a3 Special treatment for the bank overlap metric 2016-05-31 17:06:38 +02:00
Éder F. Zulian
21aab5eb0b Special treatment for the bank overlap metric. 
Our C++ python interface expects a single return value from the python script
for each metric.
 2016-05-31 16:41:26 +02:00
Frederik Lauer
8f7c854df3 Merge commit '7722471b5ae36275fd3617980a172c38239e26ef' into Bandwidth_Edit 2016-05-31 13:56:59 +02:00
Frederik Lauer
e45b2afc40 typos Fixes 2016-05-31 11:54:52 +02:00
Frederik Lauer
f69aad431a comment "idle time" and "active time" out 2016-05-31 11:02:26 +02:00
Frederik Lauer
ac3051c78a Minor changes: printing values with precision 2 
printing Units without [ ]
 2016-05-31 00:23:10 +02:00
Frederik Lauer
30ea79f761 - new Formular for maxBandwidth 
- Indention corrected
 2016-05-30 18:18:42 +02:00
Felipe Salerno Prado
1688674eca Small Fixes 2016-05-24 11:40:57 +02:00
Felipe Salerno Prado
eba49e6594 Small Changes 2016-05-23 16:09:57 +02:00
sprado
bd5b86a142 Resolving Merge Conflicts 2016-05-23 15:54:21 +02:00
Felipe Salerno Prado
212b39e1a8 More Improvements 2016-05-19 16:32:46 +02:00
sprado
1bbce84a5f Issue #76 fixed and some improvements 2016-05-19 15:28:27 +02:00
Éder F. Zulian
7722471b5a New address mappings for DDR3 2016-05-18 15:12:37 +02:00
Éder F. Zulian
3a417e4e7c Removing unused import and code 2016-05-18 14:28:24 +02:00
Matthias Jung
5366e6dce3 new metric for parallel banks 2016-05-18 12:00:54 +02:00
Éder F. Zulian
88cf6919f7 New metric: bank usage ratio 2016-05-17 17:22:45 +02:00
Frederik Lauer
05d7c3e737 Bandwidth over time calculation 2016-05-15 21:29:24 +02:00
Frederik Lauer
120d216964 IDLE Time in Controller.h 2016-05-11 23:29:58 +02:00
Felipe Salerno Prado
fb5a49224a Simulation Progress Bar 2016-05-11 14:07:15 +02:00
Felipe Salerno Prado
87e2fce2e7 Simulation Progress Bar 2016-05-11 14:04:29 +02:00
Éder F. Zulian
604f882b5b Revert "User can choose bankwise power calculation" 
This reverts commit ab2af8c953.
 2016-05-10 20:30:18 +02:00
Éder F. Zulian
ab2af8c953 User can choose bankwise power calculation 2016-05-10 18:18:00 +02:00
fzeder
375efaadac Merge pull request #78 from fzeder/master 
Power plots generation - scales fixed.
 2016-05-10 17:36:03 +02:00
Éder F. Zulian
5371930f1a This commit reverts some changes because the plots generation was broken. 
We may reimplement such changes in the near feature considering also the new
status of DRAMSys (more specifically Dram.h) and DRAMPower.

Changes introduced in the following commits were reverted:
98249947f4
c0f83bb1dc

Other changes:
Upper and lower limits for some plots adjusted.
 2016-05-10 15:29:15 +02:00
Éder F. Zulian
e31322abe6 Merge remote-tracking branch 'upstream/master' 2016-05-10 10:12:08 +02:00
Éder F. Zulian
7225c4ee51 Project file adapted to comply with the new DRAMPower Makefile 2016-05-10 10:06:59 +02:00
Éder F. Zulian
69f40dfc48 Merge remote-tracking branch 'upstream/master' 2016-05-09 16:52:53 +02:00
Éder F. Zulian
4da56929a8 Moved DRAMPower submodule to master 2016-05-09 16:04:26 +02:00
Felipe Salerno Prado
d359ed6ac3 ARM - DRAMSys Patch 2016-05-09 15:24:27 +02:00
Felipe Salerno Prado
a88d17976a Plot bandwidth over time regardless of Power Analysis 2016-05-09 14:45:06 +02:00
Felipe Salerno Prado
dba53cd3e6 Merge branch 'master' of https://git.rhrk.uni-kl.de/sprado/dram.vp.system 2016-05-09 14:04:32 +02:00
Felipe Salerno Prado
1dfbbf62ce Choose the number of samples instead of the size of the time window 2016-05-09 13:59:59 +02:00
Matthias Jung
f361df62fb First trace generator for Bankwise-DRAMPower experiments 2016-05-06 11:03:26 +02:00
Matthias Jung
4edb3978fe small fixes for MAC 2016-05-04 11:32:28 +02:00
Matthias Jung
a02dd8350a Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2016-05-04 10:57:27 +02:00
Matthias Jung
eab6c3bcc2 Debug mode default off 2016-05-04 10:57:10 +02:00
Matthias Jung
2167649bfc Created an online bandwith calculation 
This is just a preliminary implementation
 2016-05-04 10:55:05 +02:00
Éder F. Zulian
8e4e9f4f65 Typo fixed 2016-05-03 17:24:12 +02:00
Éder F. Zulian
932c8df066 Merge remote-tracking branch 'upstream/master' 2016-05-03 17:12:27 +02:00
fzeder
afd06aa709 Merge pull request #80 from sprado/master 
Charts Correction
 2016-05-03 17:03:19 +02:00
Felipe Salerno Prado
c0f83bb1dc Charts Correction 2016-04-28 17:22:40 +02:00
Felipe Salerno Prado
bdc9e58d60 Charts Correction 2016-04-28 17:17:26 +02:00
sprado
98249947f4 Charts Correction 2016-04-28 15:27:32 +02:00
Éder F. Zulian
997d11286c Using the same function to convert clk freq. to period for all memories. 2016-04-24 17:26:42 +02:00
Éder F. Zulian
e07445a58e Using average power values directly from DRAMPower. 
Now we store the average power values directly obtained from the DRAMPower
library into the database. Thus we do not have to divide energy by time to
calculate them anymore (avoiding any possible lost of accuracy due to
rounding).

Other changes:
- At the very beginning (zero clock cycles) the energy is 0, so the
  powerWindow thread wait first.

- When working with floats, we have to decide ourselves what is an acceptable
  definition for "equal". Now we compare the energy value with a suitable
  error margin (0.00001). Now the assertion that ensures the energy is not
  zero is working properly.

Notes:
- The assert() function does nothing if NDEBUG is defined.

- The total energy is provided by DRAMPower as a double. We accumulate the
  total energy for every window since we are clearing the library counters.

  Explanation about double precision:
  The double type ensures 15 decimal digits to represent a number. It does not
  matter if the digits are before or after the comma. Thus we only have
  rounding for numbers represented with more than 15 decimal digits.

  In more technical terms:
  An IEEE double has 53 significant bits (see also DBL_MANT_DIG in <cfloat>).
  That is approximately 15.95 decimal digits (log10(2^53)). The implementation
  sets the number of digits (DBL_DIG) to 15, not 16, because it has to round
  down.
 2016-04-22 11:50:39 +02:00