derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Created an online bandwith calculation

Browse Source 
This is just a preliminary implementation
This commit is contained in:
Matthias Jung
2016-05-04 10:55:05 +02:00
parent c6b61d39e9
commit 2167649bfc
1 changed files with 34 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
DRAMSys/simulator/src/simulation/Dram.h
View File

@@ -74,6 +74,11 @@ struct Dram : sc_module
double totalEnergy = 0;
double sumOfEnergyWindows = 0;
// Bandwith realted:
unsigned long long int numberOfTransactionsServed;
sc_time firstAccess;
sc_time lastAccess;
// Error Model related:
ErrorStorageMode ErrorStoreMode = Configuration::getInstance().ErrorStoreMode;
std::vector<errorModel *> ememory;
@@ -175,6 +180,11 @@ struct Dram : sc_module
SC_THREAD(powerWindow);
}
// Bandwidth Calculation:
numberOfTransactionsServed = 0;
firstAccess = SC_ZERO_TIME;
lastAccess = SC_ZERO_TIME;
printDebugMessage(string("ErrorStorageMode: ") + EnumToString(ErrorStoreMode));
// For each bank in a channel a error Model is created:
@@ -213,9 +223,17 @@ struct Dram : sc_module
assert(sumOfEnergyWindows == totalEnergy);
// Print Final Total Power Values:
cout << name() << string("\tTotal Energy: \t") + to_string(totalEnergy) << endl;
cout << name() << string("\tAverage Power: \t") + to_string(DRAMPower->getPower().average_power) << endl;
cout << name() << string("\tTotal Energy: \t") + to_string(totalEnergy) << " pJ"<< endl;
cout << name() << string("\tAverage Power: \t") + to_string(DRAMPower->getPower().average_power) << " mW"<< endl;
}
// Bandwidth:
sc_time activeTime = numberOfTransactionsServed * Configuration::getInstance().memSpec.BurstLength / Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.clk;
double bandwidth = (activeTime/(lastAccess-firstAccess)*100);
cout << name() << string("\tTotal Bandwidth: \t") + to_string(bandwidth) << " %" << endl;
cout << name() << string("\tTotal Bandwidth/IDLE: \tTODO %") << endl;
// Clean up:
for (auto e : ememory) {
delete e;
@@ -253,6 +271,16 @@ struct Dram : sc_module
// Recording time used by the traceAnalyzer
sc_time recTime = sc_time_stamp() + delay;
if(numberOfTransactionsServed == 0)
{
firstAccess = sc_time_stamp();
}
else
{
lastAccess = sc_time_stamp();
}
// These are terminating phases recorded by the DRAM. The execution
// time of the related command must be taken into consideration.
if (phase == END_PDNA || phase == END_PDNAB) {
@@ -298,6 +326,7 @@ struct Dram : sc_module
else if (phase == BEGIN_WR)
{
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WR, bank, cycle);}
numberOfTransactionsServed++;
//save data:
if (ErrorStoreMode == ErrorStorageMode::NoStorage)
@@ -316,6 +345,7 @@ struct Dram : sc_module
}
else if (phase == BEGIN_RD)
{
numberOfTransactionsServed++;
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RD, bank, cycle);}
// Load data:
@@ -339,6 +369,7 @@ struct Dram : sc_module
}
else if (phase == BEGIN_WRA)
{
numberOfTransactionsServed++;
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::WRA, bank, cycle);}
//save data:
@@ -358,6 +389,7 @@ struct Dram : sc_module
}
else if (phase == BEGIN_RDA)
{
numberOfTransactionsServed++;
if(powerAnalysis == true){DRAMPower->doCommand(MemCommand::RDA, bank, cycle);}
// Load data: