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Merge remote branch 'upstream/master'

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This commit is contained in:
Felipe Salerno Prado
2016-06-01 14:34:27 +02:00
parent 655ef76a6c 417b454726
commit c61a41daf5
5 changed files with 116 additions and 19 deletions
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68
DRAMSys/simulator/src/controller/Controller.h
View File

@@ -88,11 +88,16 @@ public:
~Controller()
{
delete controllerCore;
delete controllerCore;
delete scheduler;
}
void terminateSimulation();
sc_time getIdleTime();
sc_time getEndTime();
sc_time getStartTime();
// ------- CONTROLLER CORE ---------
virtual void send(const ScheduledCommand& command, tlm_generic_payload& payload) override;
virtual void send(Trigger trigger, sc_time time, tlm_generic_payload& payload) override;
@@ -138,6 +143,17 @@ private:
DebugManager& debugManager;
TlmRecorder *tlmRecorder;
// Bandwidth realted:
sc_time idleStart;
bool idleState = false;
sc_time idleTime;
sc_time endTime;
sc_time startTime;
int startTimeSet = false;
void startBandwidthIdleCollector();
void endBandwidthIdleCollector();
};
// --- IMPLEMENTATION -----
@@ -353,6 +369,11 @@ tlm_sync_enum Controller<BUSWIDTH>::nb_transport_fw(tlm_generic_payload &payload
tlmRecorder->recordPhase(payload, phase, recTime);
frontendPEQ.notify(payload, phase, notDelay);
//Bandwidth IDLE
if ((getTotalNumberOfPayloadsInSystem()== 0)&& idleState){
endBandwidthIdleCollector();
}
}
else if (phase == END_RESP)
{
@@ -361,6 +382,11 @@ tlm_sync_enum Controller<BUSWIDTH>::nb_transport_fw(tlm_generic_payload &payload
printDebugMessage("[fw] Recording " + phaseNameToString(phase) + " at " + recTime.to_string() + " notification in " + notDelay.to_string());
// Badnwith IDLE
if (getTotalNumberOfPayloadsInSystem()==1){
startBandwidthIdleCollector();
}
tlmRecorder->recordPhase(payload, phase, recTime);
frontendPEQ.notify(payload, phase, notDelay);
}
@@ -378,6 +404,7 @@ void Controller<BUSWIDTH>::frontendPEQCallback(tlm_generic_payload &payload, con
{
if (phase == BEGIN_REQ)
{
printDebugMessage(string("Payload in system: ") + to_string(getTotalNumberOfPayloadsInSystem()));
payload.acquire();
payloadEntersSystem(payload);
if (getTotalNumberOfPayloadsInSystem() > controllerCore->config.MaxNrOfTransactions)
@@ -422,6 +449,12 @@ void Controller<BUSWIDTH>::payloadEntersSystem(tlm_generic_payload &payload)
"Payload enters system on bank " + to_string(bank.ID()) + ". Total number of payloads in Controller: "
+ to_string(getTotalNumberOfPayloadsInSystem()));
numberOfPayloadsInSystem[bank]++;
// Set Start Time for Simulation
if (startTimeSet == false){
printDebugMessage("Simulation Timer Start");
startTime = sc_time_stamp()-Configuration::getInstance().memSpec.clk;
startTimeSet = true;
}
}
template<unsigned int BUSWIDTH>
@@ -454,7 +487,7 @@ void Controller<BUSWIDTH>::scheduleNextFromScheduler(Bank bank)
{
return;
}
pair<Command, tlm::tlm_generic_payload*> nextRequest = scheduler->getNextRequest(bank);
if(nextRequest.second != NULL)
{
@@ -598,5 +631,36 @@ void Controller<BUSWIDTH>::terminateSimulation()
}
}
template<unsigned int BUSWIDTH>
void Controller<BUSWIDTH>::startBandwidthIdleCollector(){
printDebugMessage("IDLE Start");
idleStart = sc_time_stamp();
endTime = sc_time_stamp();
idleState = true;
}
template<unsigned int BUSWIDTH>
void Controller<BUSWIDTH>::endBandwidthIdleCollector(){
printDebugMessage("IDLE End");
idleTime += sc_time_stamp()-idleStart+ Configuration::getInstance().memSpec.clk;
idleState = false;
}
template<unsigned int BUSWIDTH>
sc_time Controller<BUSWIDTH>::getIdleTime(){
printDebugMessage("IDLE Time: "+idleTime.to_string());
return idleTime;
}
template<unsigned int BUSWIDTH>
sc_time Controller<BUSWIDTH>::getEndTime(){
printDebugMessage("End Time: "+endTime.to_string());
return endTime;
}
template<unsigned int BUSWIDTH>
sc_time Controller<BUSWIDTH>::getStartTime(){
printDebugMessage("Start Time: "+startTime.to_string());
return startTime;
}
#endif /* CONTROLLERWRAPPER_H_ */

31
DRAMSys/simulator/src/simulation/Dram.h
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@@ -48,6 +48,7 @@
#include <cassert>
#include "../common/DebugManager.h"
#include "../common/dramExtension.h"
#include "../controller/Controller.h"
#include "../controller/core/TimingCalculation.h"
#include "../controller/core/configuration/Configuration.h"
#include "../common/protocol.h"
@@ -72,7 +73,7 @@ struct Dram : sc_module
libDRAMPower *DRAMPower;
double sumOfEnergyWindows = 0.0;
// Bandwith realted:
// Bandwidth realted:
unsigned long long int numberOfTransactionsServed;
sc_time firstAccess;
sc_time lastAccess;
@@ -85,6 +86,7 @@ struct Dram : sc_module
map< unsigned long int, std::array<unsigned char, BUSWIDTH/2> > memory;
TlmRecorder *tlmRecorder;
Controller<>* dramController;
SC_CTOR(Dram) : tSocket("socket")
{
@@ -214,17 +216,26 @@ struct Dram : sc_module
tlmRecorder->recordPower(sc_time_stamp().to_seconds(), DRAMPower->getPower().average_power);
// Print the final total energy and the average power for the simulation
cout << name() << string("\tTotal Energy: \t") + to_string(totalEnergy) + string("\t[pJ]") << endl;
cout << name() << string("\tAverage Power: \t") + to_string(averagePower) + string("\t[mW]") << endl;
cout << name() << string("\tTotal Energy: \t") << fixed <<std::setprecision( 2 )<< totalEnergy << string(" pJ") << endl;
cout << name() << string("\tAverage Power: \t") << fixed <<std::setprecision( 2 )<< averagePower<< string(" mW") << endl;
}
// Bandwidth:
sc_time activeTime = numberOfTransactionsServed * Configuration::getInstance().memSpec.BurstLength / Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.clk;
double bandwidth = (activeTime/(lastAccess-firstAccess)*100);
cout << name() << string("\tTotal Bandwidth: \t") + to_string(bandwidth) << " %" << endl;
cout << name() << string("\tTotal Bandwidth/IDLE: \tTODO %") << endl;
sc_time idleTime = dramController->getIdleTime();
sc_time endTime = dramController->getEndTime();
sc_time startTime = dramController->getStartTime();
double bandwidth = (activeTime/(endTime-startTime)*100);
double bandwidth_IDLE = ((activeTime)/(endTime-startTime-idleTime)*100);
// | clk in Mhz e.g. 800 [MHz] | * | DataRate e.g. 2 | * | BusWidth e.g. 8 | / | 1024 |
double maxBandwidth = ( (1000000/Configuration::getInstance().memSpec.clk.to_double()) * Configuration::getInstance().memSpec.DataRate * Configuration::getInstance().memSpec.BusWidth ) / ( 1024 );
cout << name() << string("\tTotal Time: \t") <<(endTime-startTime).to_string() << endl;
//cout << name() << string("\tTotal IDLE: \t") <<idleTime.to_string() << endl;
//cout << name() << string("\tTotal Active DataBus: \t") << activeTime.to_string() << endl;
cout << name() << string("\tAVG BW: \t") <<std::fixed<<std::setprecision(2) << ((bandwidth/100)*maxBandwidth) << " GiB/s (" << bandwidth << " %)" << endl;
cout << name() << string("\tAVG BW/IDLE: \t") <<std::fixed<<std::setprecision(2) << ((bandwidth_IDLE/100)*maxBandwidth) <<" GiB/s ("<< (bandwidth_IDLE) << " %)" << endl;
cout << name() << string("\tMAX BW: \t") <<std::fixed<<std::setprecision(2) <<maxBandwidth << " GiB/s" << endl;
// Clean up:
for (auto e : ememory) {
delete e;
@@ -570,6 +581,10 @@ struct Dram : sc_module
{
tlmRecorder = rec;
}
void setDramController(Controller<> *contr)
{
dramController = contr;
}
};
#endif /* DRAM_H_ */

2
DRAMSys/simulator/src/simulation/Simulation.cpp
View File

@@ -49,6 +49,7 @@
#include "../common/Utils.h"
#include "../simulation/StlDataPlayer.h"
#include "../simulation/TemperatureController.h"
#include "../controller/Controller.h"
using namespace std;
@@ -153,6 +154,7 @@ void Simulation::instantiateModules(const string &traceName, const string &pathT
str = "dram" + std::to_string(i);
Dram<> *dram = new Dram<>(str.c_str());
dram->setTlmRecorder(tlmRecorders[i]);
dram->setDramController(controllers[i]);
drams.push_back(dram);
}
}

32
DRAMSys/tests/simple/expected.txt
View File

@@ -1,9 +1,25 @@
Info: /OSCI/SystemC: Simulation stopped by user.
sim.dram0 Total Energy: 4300303.748256
sim.dram0 Average Power: 12.617304
sim.dram1 Total Energy: 2157481.552032
sim.dram1 Average Power: 6.404758
sim.dram2 Total Energy: 4202780.152032
sim.dram2 Average Power: 12.337053
sim.dram3 Total Energy: 2293679.842704
sim.dram3 Average Power: 6.809080
sim.dram0 Total Energy: 4300303.75 pJ
sim.dram0 Average Power: 12.61 mW
sim.dram0 Total Time: 340669248 ps
sim.dram0 AVG BW: 1.00 GiB/s (4.81 %)
sim.dram0 AVG BW/IDLE: 10.64 GiB/s (51.27 %)
sim.dram0 MAX BW: 20.75 GiB/s
sim.dram1 Total Energy: 2173431.43 pJ
sim.dram1 Average Power: 6.37 mW
sim.dram1 Total Time: 0 s
sim.dram1 AVG BW: -nan GiB/s (-nan %)
sim.dram1 AVG BW/IDLE: -nan GiB/s (-nan %)
sim.dram1 MAX BW: 20.75 GiB/s
sim.dram2 Total Energy: 4202780.15 pJ
sim.dram2 Average Power: 12.33 mW
sim.dram2 Total Time: 340115040 ps
sim.dram2 AVG BW: 0.75 GiB/s (3.63 %)
sim.dram2 AVG BW/IDLE: 15.65 GiB/s (75.44 %)
sim.dram2 MAX BW: 20.75 GiB/s
sim.dram3 Total Energy: 2309629.72 pJ
sim.dram3 Average Power: 6.77 mW
sim.dram3 Total Time: 312862464 ps
sim.dram3 AVG BW: 0.03 GiB/s (0.14 %)
sim.dram3 AVG BW/IDLE: 9.21 GiB/s (44.40 %)
sim.dram3 MAX BW: 20.75 GiB/s

2
DRAMSys/tests/simple/test.pl
View File

@@ -44,7 +44,7 @@ chdir("../../../build/simulator/");
chdir("../../DRAMSys/tests/simple");
`cat output.txt | tail -n 9 > current.txt`;
`cat output.txt | tail -n 25 > current.txt`;
if(compare("current.txt","expected.txt") == 0)
{