Commit Graph

2819 Commits

Author SHA1 Message Date
Jonathan Hager
950dbd690d Removed DramRecordable import 2025-03-26 13:58:14 +01:00
Jonathan Hager
94954c8697 Switch from shared_ptrs back to references
Dram and Controller hold a const pointer instead of a reference, so that
it can be set to null, if database recording is disabled
2025-03-26 13:53:23 +01:00
Jonathan Hager
d773abc7ce Updated unit tests for HBM2
This is necessary, as recording the phases with tlmRecorders on the bus
changed the internal call order in the SystemC kernel. This leads to
different IDs in the database
2025-03-26 13:53:23 +01:00
Jonathan Hager
9c690c021c Fixed nullptr segfault if no database recording
Dram and Controller handle this case now and are initialized with a
shared_ptr pointing to null
2025-03-26 13:53:22 +01:00
Jonathan Hager
2f8c318c0e Implemented b_transport and dbg 2025-03-26 13:53:22 +01:00
Jonathan Hager
d349aafff7 Change TlmRecorderArbiter to TlmRecorderController 2025-03-26 13:53:22 +01:00
Jonathan Hager
86281cc6d3 Removed ControllerRecordable 2025-03-26 13:53:22 +01:00
Jonathan Hager
5b7dcbcc1c Moved TlmRecorder from reference to smart pointer 2025-03-26 13:53:22 +01:00
Jonathan Hager
0479184f72 Split the bandwidth recording in two modules
This allows separate recording of the bandwidth between Arbiter -
Controller and Controller - Dram
2025-03-26 13:53:22 +01:00
Jonathan Hager
f1445ab851 WIP: Moved BufferDepth out of ControllerRecordable 2025-03-26 13:53:22 +01:00
Jonathan Hager
9a563e78d5 Moved Bandwidth recording out of the Controller 2025-03-26 13:53:22 +01:00
Jonathan Hager
c45137958d Removed DramRecordable 2025-03-26 13:53:11 +01:00
Jonathan Hager
d5862e55ea Moved DramRecordable logic to Dram 2025-03-26 13:52:19 +01:00
Jonathan Hager
0975e52f5f Changed TlmRecorderWrapper to simple_sockets 2025-03-26 13:52:19 +01:00
Jonathan Hager
8b64cbf047 Added TlmRecorderWrapper to handle database logic 2025-03-26 13:52:18 +01:00
1ad352aa8b Merge branch 'fix/trafficgeneratordelays' into 'develop'
Fix delays in traffic generators

See merge request ems/astdm/modeling.dram/dram.sys.5!113
2025-03-26 09:04:21 +00:00
c1f4655d19 Fix delays in traffic generators 2025-03-26 09:59:51 +01:00
dc81bc008a Make tool out of json_converter 2025-03-26 09:08:36 +01:00
391b4cdb82 Merge branch 'fix/forward_declare_dram' into 'develop'
Fix the forward declaration of the Dram class

See merge request ems/astdm/modeling.dram/dram.sys.5!111
2025-03-25 18:31:08 +00:00
98eae7fcf4 Fix the forward declaration of the Dram class 2025-03-25 19:18:09 +01:00
aafb704cf8 Use std::optional in cmdMux 2025-03-24 13:39:50 +01:00
ace395bf89 Merge branch 'export_preset' into 'develop'
Enable compile command export in CMakePresets

See merge request ems/astdm/modeling.dram/dram.sys.5!107
2025-03-14 13:18:48 +00:00
eead4afbdd Enable compile command export in CMakePresets 2025-03-14 14:18:12 +01:00
35c6716dd2 Merge branch 'fix/james_hbm_sid' into 'develop'
Fix issue with stack id

See merge request ems/astdm/modeling.dram/dram.sys.5!105
2025-03-03 16:02:56 +00:00
e9643e7938 Fix issue with stack id 2025-03-03 16:58:51 +01:00
4a627c3c6c Merge branch 'fix/gem5_alignment' into 'develop'
Fix gem5 memory alignment

See merge request ems/astdm/modeling.dram/dram.sys.5!93
2025-02-27 14:12:16 +00:00
dbb6636c5a Fix LPDDR4 and LPDDR5 regression tests 2025-02-26 17:10:11 +01:00
76e8dba113 Do not align address to minimum burst length 2025-02-26 17:10:11 +01:00
ab35483aec Merge branch 'fix/ta_db_not_existing' into 'develop'
Do not create empty database file when it does not exist

See merge request ems/astdm/modeling.dram/dram.sys.5!104
2025-02-26 08:35:26 +00:00
5b76e52cd4 Do not create empty database file when it does not exist 2025-02-26 09:28:36 +01:00
7431f79ac3 Use proprietary license text in extension files 2025-02-21 15:11:37 +01:00
e691d46a55 Merge branch 'fix/tCCDR_HBM2' into 'develop'
Implement tCCDR for HBM2 and fix bug with SID

See merge request ems/astdm/modeling.dram/dram.sys.5!102
2025-02-21 14:08:16 +00:00
6861576550 Implement tCCDR for HBM2 and fix bug with SID 2025-02-21 14:18:30 +01:00
5ab5a70d65 Merge branch 'fix/cxx_std' into 'develop'
Fix SystemC C++ std

See merge request ems/astdm/modeling.dram/dram.sys.5!101
2025-02-13 10:41:30 +00:00
2b52bff6c6 Fix SystemC C++ std 2025-02-13 11:37:51 +01:00
4a2c1b28b5 Merge branch 'fix/cxx_std' into 'develop'
When project is top-level, force C++17

See merge request ems/astdm/modeling.dram/dram.sys.5!100
2025-02-13 10:33:08 +00:00
b9fc47d1fe When project is top-level, force C++17 2025-02-13 11:14:55 +01:00
Lukas Steiner
f223e6c500 Merge branch 'feat/hbm3_sid' into 'develop'
Feat/hbm3 sid

See merge request ems/astdm/modeling.dram/dram.sys.5!96
2025-01-28 09:04:16 +00:00
Lukas Steiner
35fa3b18c9 Merge branch 'feat/thinkdelay' into 'develop'
Use think delay as miminum END_REQ delay

See merge request ems/astdm/modeling.dram/dram.sys.5!98
2025-01-28 09:02:13 +00:00
e57ce9cc86 Use controller clock as interface clock in initiators 2025-01-24 15:55:40 +01:00
581794b970 Allow responses to be sent back-to-back 2025-01-24 14:58:06 +01:00
ba94d9fd84 Have a one cycle END_RESP delay in the standard initiator 2025-01-24 14:43:06 +01:00
1225f6b044 Fix tests after ThinkDelayFw 2025-01-24 14:19:53 +01:00
0a478dbdc5 Issue a warning if ThinkDelayFw is 0 2025-01-24 14:18:40 +01:00
007c55e878 Use think delay as miminum END_REQ delay
When the controller accepts requests in the same clock cycle as it
handles them, undeterministic simulations can occur as the outcome
depends on if the new request is accepted before the controllerMethod
is called or not.

Therefore, a minimum delay of one clock cylce should be used to always
handle request only in the next clock cycle, removing the disambiguity.
2025-01-24 14:18:39 +01:00
Lukas Steiner
1b50709591 Merge branch 'feat/new_checkers' into 'develop'
Use new timing checkers

See merge request ems/astdm/modeling.dram/dram.sys.5!95
2025-01-17 14:23:24 +00:00
a68a0c9ded Restore brc HBM3 mapping 2025-01-16 15:39:04 +01:00
e5ca7f1229 Merge branch 'fix/generator_parameters' into 'develop'
Fix the verification of generator parameters

See merge request ems/astdm/modeling.dram/dram.sys.5!97
2025-01-14 13:59:41 +00:00
d71e649447 Fix the verification of generator parameters
Also, clamp the read write ratio instead of generating an error
2025-01-14 14:55:11 +01:00
7a8633d36e Implement stack ID for HBM3 2025-01-13 15:36:05 +01:00