Merge branch 'fix/gem5_alignment' into 'develop'
Fix gem5 memory alignment See merge request ems/astdm/modeling.dram/dram.sys.5!93
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@@ -552,16 +552,16 @@ void Controller::manageRequests(const sc_time& delay)
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transToAcquire.payload->acquire();
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// Align address to minimum burst length
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uint64_t alignedAddress =
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transToAcquire.payload->get_address() & ~(minBytesPerBurst - UINT64_C(1));
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transToAcquire.payload->set_address(alignedAddress);
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// The following logic assumes that transactions are naturally aligned
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const uint64_t address = transToAcquire.payload->get_address();
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const uint64_t dataLength = transToAcquire.payload->get_data_length();
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assert((dataLength & (dataLength - 1)) == 0); // Data length must be a power of 2
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assert(address % dataLength == 0); // Check if naturally aligned
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// continuous block of data that can be fetched with a single burst
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if ((alignedAddress / maxBytesPerBurst) ==
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((alignedAddress + transToAcquire.payload->get_data_length() - 1) /
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maxBytesPerBurst))
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if ((address / maxBytesPerBurst) ==
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((address + transToAcquire.payload->get_data_length() - 1) / maxBytesPerBurst))
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{
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// continuous block of data that can be fetched with a single burst
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DecodedAddress decodedAddress =
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addressDecoder.decodeAddress(transToAcquire.payload->get_address());
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ControllerExtension::setAutoExtension(*transToAcquire.payload,
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@@ -124,7 +124,7 @@
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"Debug": false,
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"EnableWindowing": false,
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"PowerAnalysis": false,
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"SimulationName": "example",
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"SimulationName": "lpddr5",
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"SimulationProgressBar": true,
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"StoreMode": "NoStorage",
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"UseMalloc": false,
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