Merge branch 'fix/gem5_alignment' into 'develop'

Fix gem5 memory alignment

See merge request ems/astdm/modeling.dram/dram.sys.5!93
This commit is contained in:
2025-02-27 14:12:16 +00:00
6 changed files with 15 additions and 12 deletions

View File

@@ -552,16 +552,16 @@ void Controller::manageRequests(const sc_time& delay)
transToAcquire.payload->acquire();
// Align address to minimum burst length
uint64_t alignedAddress =
transToAcquire.payload->get_address() & ~(minBytesPerBurst - UINT64_C(1));
transToAcquire.payload->set_address(alignedAddress);
// The following logic assumes that transactions are naturally aligned
const uint64_t address = transToAcquire.payload->get_address();
const uint64_t dataLength = transToAcquire.payload->get_data_length();
assert((dataLength & (dataLength - 1)) == 0); // Data length must be a power of 2
assert(address % dataLength == 0); // Check if naturally aligned
// continuous block of data that can be fetched with a single burst
if ((alignedAddress / maxBytesPerBurst) ==
((alignedAddress + transToAcquire.payload->get_data_length() - 1) /
maxBytesPerBurst))
if ((address / maxBytesPerBurst) ==
((address + transToAcquire.payload->get_data_length() - 1) / maxBytesPerBurst))
{
// continuous block of data that can be fetched with a single burst
DecodedAddress decodedAddress =
addressDecoder.decodeAddress(transToAcquire.payload->get_address());
ControllerExtension::setAutoExtension(*transToAcquire.payload,

View File

@@ -124,7 +124,7 @@
"Debug": false,
"EnableWindowing": false,
"PowerAnalysis": false,
"SimulationName": "example",
"SimulationName": "lpddr5",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"UseMalloc": false,