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Merge branch 'feat/thinkdelay' into 'develop'

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Use think delay as miminum END_REQ delay

See merge request ems/astdm/modeling.dram/dram.sys.5!98
This commit is contained in:
Lukas Steiner
2025-01-28 09:02:13 +00:00
parent 1b50709591 e57ce9cc86
commit 35fa3b18c9
20 changed files with 90 additions and 102 deletions
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18
configs/README.md
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@@ -313,3 +313,21 @@ An example follows.
- maximum number of active transactions per initiator (only applies to "Fifo" and "Reorder" arbiter policy)
- *RefreshManagement* (boolean)
- enable the sending of refresh management commands when the number of activates to one bank exceeds a certain management threshold (only supported in DDR5 and LPDDR5)
- *ArbitrationDelayFw* (unsigned int)
- number of clock cycles spent in forward arbitration to channel controllers
- *ArbitrationDelayBw* (unsigned int)
- number of clock cycles spent in backward arbitration to initiator
- *ThinkDelayFw* (unsigned int)
- minimum number of clock cycles between acceptance of a request to command issuance
- *ThinkDelayBw* (unsigned int)
- minimum number of clock cycles until response is forwarded to the arbiter
- *PhyDelayFw* (unsigned int)
- number of clock cycles between command issuance and occupation on the command/data bus
- *PhyDelayBw* (unsigned int)
- number of clock cycles between read data on the data bus and arrival in the channel controller
- *BlockingReadDelay* (unsigned int)
- constant number of clock cycles spent reading data in blocking mode
- **warning**: usage of blocking transport produces in inaccurate simulation results
- *BlockingWriteDelay* (unsigned int)
- constant number of clock cycles spent writing data in blocking mode
- **warning**: usage of blocking transport produces in inaccurate simulation results

22
src/libdramsys/DRAMSys/controller/Controller.cpp
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@@ -422,7 +422,7 @@ void Controller::controllerMethod()
scheduler->removeRequest(*trans);
manageRequests(config.thinkDelayFw);
respQueue->insertPayload(trans,
sc_time_stamp() + config.thinkDelayFw + config.phyDelayFw +
sc_time_stamp() + config.phyDelayFw +
memSpec.getIntervalOnDataStrobe(command, *trans).end +
config.phyDelayBw + config.thinkDelayBw);
@@ -435,7 +435,7 @@ void Controller::controllerMethod()
if (ranksNumberOfPayloads[rank] == 0)
powerDownManagers[rank]->triggerEntry();
sc_time fwDelay = config.thinkDelayFw + config.phyDelayFw;
sc_time fwDelay = config.phyDelayFw;
tlm_phase phase = command.toPhase();
iSocket->nb_transport_fw(*trans, phase, fwDelay);
}
@@ -501,8 +501,8 @@ Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_tim
if (phase == BEGIN_REQ)
{
transToAcquire.payload = &trans;
transToAcquire.arrival = sc_time_stamp() + delay;
beginReqEvent.notify(delay);
transToAcquire.arrival = sc_time_stamp() + delay + config.thinkDelayFw;
beginReqEvent.notify(delay + config.thinkDelayFw);
}
else if (phase == END_RESP)
{
@@ -659,12 +659,7 @@ void Controller::manageResponses()
{
transToRelease.payload = &parentTrans;
tlm_phase bwPhase = BEGIN_RESP;
sc_time bwDelay;
if (transToRelease.arrival ==
sc_time_stamp()) // last payload was released in this cycle
bwDelay = memSpec.tCK;
else
bwDelay = SC_ZERO_TIME;
sc_time bwDelay = SC_ZERO_TIME;
sendToFrontend(*transToRelease.payload, bwPhase, bwDelay);
transToRelease.arrival = scMaxTime;
@@ -680,12 +675,7 @@ void Controller::manageResponses()
{
transToRelease.payload = nextTransInRespQueue;
tlm_phase bwPhase = BEGIN_RESP;
sc_time bwDelay;
if (transToRelease.arrival ==
sc_time_stamp()) // last payload was released in this cycle
bwDelay = memSpec.tCK;
else
bwDelay = SC_ZERO_TIME;
sc_time bwDelay = SC_ZERO_TIME;
sendToFrontend(*transToRelease.payload, bwPhase, bwDelay);
transToRelease.arrival = scMaxTime;

38
src/libdramsys/DRAMSys/controller/McConfig.cpp
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@@ -57,23 +57,14 @@ McConfig::McConfig(const Config::McConfig& config, const MemSpec& memSpec) :
powerDownPolicy(config.PowerDownPolicy.value_or(DEFAULT_POWER_DOWN_POLICY)),
maxActiveTransactions(config.MaxActiveTransactions.value_or(DEFAULT_MAX_ACTIVE_TRANSACTIONS)),
refreshManagement(config.RefreshManagement.value_or(DEFAULT_REFRESH_MANAGEMENT)),
arbitrationDelayFw(sc_core::sc_time(
config.ArbitrationDelayFw.value_or(DEFAULT_ARBITRATION_DELAY_FW_NS), sc_core::SC_NS)),
arbitrationDelayBw(sc_core::sc_time(
config.ArbitrationDelayBw.value_or(DEFAULT_ARBITRATION_DELAY_BW_NS), sc_core::SC_NS)),
thinkDelayFw(
sc_core::sc_time(config.ThinkDelayFw.value_or(DEFAULT_THINK_DELAY_FW_NS), sc_core::SC_NS)),
thinkDelayBw(
sc_core::sc_time(config.ThinkDelayBw.value_or(DEFAULT_THINK_DELAY_BW_NS), sc_core::SC_NS)),
phyDelayFw(
sc_core::sc_time(config.PhyDelayFw.value_or(DEFAULT_PHY_DELAY_FW_NS), sc_core::SC_NS)),
phyDelayBw(
sc_core::sc_time(config.PhyDelayBw.value_or(DEFAULT_PHY_DELAY_BW_NS), sc_core::SC_NS)),
blockingReadDelay(sc_core::sc_time(
config.BlockingReadDelay.value_or(DEFAULT_BLOCKING_READ_DELAY_NS), sc_core::SC_NS)),
blockingWriteDelay(sc_core::sc_time(
config.BlockingWriteDelay.value_or(DEFAULT_BLOCKING_WRITE_DELAY_NS), sc_core::SC_NS))
arbitrationDelayFw(config.ArbitrationDelayFw.value_or(DEFAULT_ARBITRATION_DELAY_FW) * memSpec.tCK),
arbitrationDelayBw(config.ArbitrationDelayBw.value_or(DEFAULT_ARBITRATION_DELAY_BW) * memSpec.tCK),
thinkDelayFw(config.ThinkDelayFw.value_or(DEFAULT_THINK_DELAY_FW) * memSpec.tCK),
thinkDelayBw(config.ThinkDelayBw.value_or(DEFAULT_THINK_DELAY_BW) * memSpec.tCK),
phyDelayFw(config.PhyDelayFw.value_or(DEFAULT_PHY_DELAY_FW) * memSpec.tCK),
phyDelayBw(config.PhyDelayBw.value_or(DEFAULT_PHY_DELAY_BW) * memSpec.tCK),
blockingReadDelay(config.BlockingReadDelay.value_or(DEFAULT_BLOCKING_READ_DELAY) * memSpec.tCK),
blockingWriteDelay(config.BlockingWriteDelay.value_or(DEFAULT_BLOCKING_WRITE_DELAY) * memSpec.tCK)
{
if (schedulerBuffer == Config::SchedulerBufferType::ReadWrite &&
config.RequestBufferSize.has_value())
@@ -116,17 +107,8 @@ McConfig::McConfig(const Config::McConfig& config, const MemSpec& memSpec) :
if (requestBufferSizeWrite < 1)
SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!");
arbitrationDelayFw = std::round(arbitrationDelayFw / memSpec.tCK) * memSpec.tCK;
arbitrationDelayBw = std::round(arbitrationDelayBw / memSpec.tCK) * memSpec.tCK;
thinkDelayFw = std::round(thinkDelayFw / memSpec.tCK) * memSpec.tCK;
thinkDelayBw = std::round(thinkDelayBw / memSpec.tCK) * memSpec.tCK;
phyDelayFw = std::round(phyDelayFw / memSpec.tCK) * memSpec.tCK;
phyDelayBw = std::round(phyDelayBw / memSpec.tCK) * memSpec.tCK;
blockingReadDelay = std::round(blockingReadDelay / memSpec.tCK) * memSpec.tCK;
blockingWriteDelay = std::round(blockingWriteDelay / memSpec.tCK) * memSpec.tCK;
if (thinkDelayFw == sc_core::SC_ZERO_TIME)
SC_REPORT_WARNING("Configuration", "ThinkDelayFw should at least be 1!");
}
} // namespace DRAMSys

16
src/libdramsys/DRAMSys/controller/McConfig.h
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@@ -100,14 +100,14 @@ struct McConfig
Config::PowerDownPolicyType::NoPowerDown;
static constexpr unsigned int DEFAULT_MAX_ACTIVE_TRANSACTIONS = 64;
static constexpr bool DEFAULT_REFRESH_MANAGEMENT = false;
static constexpr unsigned DEFAULT_ARBITRATION_DELAY_FW_NS = 0;
static constexpr unsigned DEFAULT_ARBITRATION_DELAY_BW_NS = 0;
static constexpr unsigned DEFAULT_THINK_DELAY_FW_NS = 0;
static constexpr unsigned DEFAULT_THINK_DELAY_BW_NS = 0;
static constexpr unsigned DEFAULT_PHY_DELAY_FW_NS = 0;
static constexpr unsigned DEFAULT_PHY_DELAY_BW_NS = 0;
static constexpr unsigned DEFAULT_BLOCKING_READ_DELAY_NS = 60;
static constexpr unsigned DEFAULT_BLOCKING_WRITE_DELAY_NS = 60;
static constexpr unsigned DEFAULT_ARBITRATION_DELAY_FW = 0;
static constexpr unsigned DEFAULT_ARBITRATION_DELAY_BW = 0;
static constexpr unsigned DEFAULT_THINK_DELAY_FW = 1;
static constexpr unsigned DEFAULT_THINK_DELAY_BW = 0;
static constexpr unsigned DEFAULT_PHY_DELAY_FW = 0;
static constexpr unsigned DEFAULT_PHY_DELAY_BW = 0;
static constexpr unsigned DEFAULT_BLOCKING_READ_DELAY = 60;
static constexpr unsigned DEFAULT_BLOCKING_WRITE_DELAY = 60;
};
} // namespace DRAMSys

4
src/simulator/simulator/SimpleInitiator.h
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@@ -43,7 +43,7 @@ template <typename Producer> class SimpleInitiator : public Initiator
public:
SimpleInitiator(sc_core::sc_module_name const& name,
MemoryManager& memoryManager,
unsigned int clkMhz,
sc_core::sc_time interfaceClk,
std::optional<unsigned int> maxPendingReadRequests,
std::optional<unsigned int> maxPendingWriteRequests,
std::function<void()> transactionFinished,
@@ -53,7 +53,7 @@ public:
issuer(
name,
memoryManager,
clkMhz,
interfaceClk,
maxPendingReadRequests,
maxPendingWriteRequests,
[this] { return this->producer.nextRequest(); },

8
src/simulator/simulator/Simulator.cpp
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@@ -84,6 +84,7 @@ std::unique_ptr<Initiator>
Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator)
{
uint64_t memorySize = dramSys->getMemSpec().getSimMemSizeInBytes();
sc_core::sc_time interfaceClk = dramSys->getMemSpec().tCK;
unsigned int defaultDataLength = dramSys->getMemSpec().defaultBytesPerBurst;
return std::visit(
@@ -94,9 +95,10 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator)
std::is_same_v<T, DRAMSys::Config::TrafficGeneratorStateMachine>)
{
return std::make_unique<TrafficGenerator>(config,
memoryManager,
interfaceClk,
memorySize,
defaultDataLength,
memoryManager,
finishTransaction,
terminateInitiator);
}
@@ -126,7 +128,7 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator)
return std::make_unique<SimpleInitiator<StlPlayer>>(config.name.c_str(),
memoryManager,
config.clkMhz,
interfaceClk,
std::nullopt,
std::nullopt,
finishTransaction,
@@ -139,7 +141,7 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator)
return std::make_unique<SimpleInitiator<RowHammer>>(config.name.c_str(),
memoryManager,
config.clkMhz,
interfaceClk,
1,
1,
finishTransaction,

13
src/simulator/simulator/generator/TrafficGenerator.cpp
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@@ -35,10 +35,14 @@
#include "TrafficGenerator.h"
#include "RandomProducer.h"
#include "SequentialProducer.h"
TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const& config,
MemoryManager& memoryManager,
sc_core::sc_time interfaceClk,
uint64_t memorySize,
unsigned int defaultDataLength,
MemoryManager& memoryManager,
std::function<void()> transactionFinished,
std::function<void()> terminateInitiator) :
stateTransistions(config.transitions),
@@ -46,7 +50,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine
issuer(
config.name.c_str(),
memoryManager,
config.clkMhz,
interfaceClk,
config.maxPendingReadRequests,
config.maxPendingWriteRequests,
[this] { return nextRequest(); },
@@ -107,16 +111,17 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine
}
TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const& config,
MemoryManager& memoryManager,
sc_core::sc_time interfaceClk,
uint64_t memorySize,
unsigned int defaultDataLength,
MemoryManager& memoryManager,
std::function<void()> transactionFinished,
std::function<void()> terminateInitiator) :
generatorPeriod(sc_core::sc_time(1.0 / static_cast<double>(config.clkMhz), sc_core::SC_US)),
issuer(
config.name.c_str(),
memoryManager,
config.clkMhz,
interfaceClk,
config.maxPendingReadRequests,
config.maxPendingWriteRequests,
[this] { return nextRequest(); },

11
src/simulator/simulator/generator/TrafficGenerator.h
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@@ -35,28 +35,31 @@
#pragma once
#include "RandomProducer.h"
#include "SequentialProducer.h"
#include "simulator/Initiator.h"
#include "simulator/MemoryManager.h"
#include "simulator/request/RequestIssuer.h"
#include <DRAMSys/config/DRAMSysConfiguration.h>
#include <random>
class RequestProducer;
class TrafficGenerator : public Initiator
{
public:
TrafficGenerator(DRAMSys::Config::TrafficGenerator const& config,
MemoryManager& memoryManager,
sc_core::sc_time interfaceClk,
uint64_t memorySize,
unsigned int defaultDataLength,
MemoryManager& memoryManager,
std::function<void()> transactionFinished,
std::function<void()> terminateInitiator);
TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const& config,
MemoryManager& memoryManager,
sc_core::sc_time interfaceClk,
uint64_t memorySize,
unsigned int defaultDataLength,
MemoryManager& memoryManager,
std::function<void()> transactionFinished,
std::function<void()> terminateInitiator);

18
src/simulator/simulator/request/RequestIssuer.cpp
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@@ -37,7 +37,7 @@
RequestIssuer::RequestIssuer(sc_core::sc_module_name const& name,
MemoryManager& memoryManager,
unsigned int clkMhz,
sc_core::sc_time interfaceClk,
std::optional<unsigned int> maxPendingReadRequests,
std::optional<unsigned int> maxPendingWriteRequests,
std::function<Request()> nextRequest,
@@ -46,7 +46,7 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const& name,
sc_module(name),
payloadEventQueue(this, &RequestIssuer::peqCallback),
memoryManager(memoryManager),
clkPeriod(sc_core::sc_time(1.0 / static_cast<double>(clkMhz), sc_core::SC_US)),
interfaceClk(interfaceClk),
maxPendingReadRequests(maxPendingReadRequests),
maxPendingWriteRequests(maxPendingWriteRequests),
transactionFinished(std::move(transactionFinished)),
@@ -85,18 +85,6 @@ void RequestIssuer::sendNextRequest()
sc_core::sc_time sendingTime = sc_core::sc_time_stamp() + delay;
bool needsOffset = (sendingTime % clkPeriod) != sc_core::SC_ZERO_TIME;
if (needsOffset)
{
sendingTime += clkPeriod;
sendingTime -= sendingTime % clkPeriod;
}
if (sendingTime == lastEndRequest)
{
sendingTime += clkPeriod;
}
delay = sendingTime - sc_core::sc_time_stamp();
iSocket->nb_transport_fw(payload, phase, delay);
@@ -136,7 +124,7 @@ void RequestIssuer::peqCallback(tlm::tlm_generic_payload& payload, const tlm::tl
else if (phase == tlm::BEGIN_RESP)
{
tlm::tlm_phase nextPhase = tlm::END_RESP;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
sc_core::sc_time delay = interfaceClk;
iSocket->nb_transport_fw(payload, nextPhase, delay);
payload.release();

8
src/simulator/simulator/request/RequestIssuer.h
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@@ -52,7 +52,7 @@ public:
RequestIssuer(sc_core::sc_module_name const& name,
MemoryManager& memoryManager,
unsigned int clkMhz,
sc_core::sc_time interfaceClk,
std::optional<unsigned int> maxPendingReadRequests,
std::optional<unsigned int> maxPendingWriteRequests,
std::function<Request()> nextRequest,
@@ -64,7 +64,7 @@ private:
tlm_utils::peq_with_cb_and_phase<RequestIssuer> payloadEventQueue;
MemoryManager& memoryManager;
const sc_core::sc_time clkPeriod;
sc_core::sc_time interfaceClk;
bool transactionPostponed = false;
bool finished = false;
@@ -75,8 +75,8 @@ private:
unsigned int pendingReadRequests = 0;
unsigned int pendingWriteRequests = 0;
const std::optional<unsigned int> maxPendingReadRequests;
const std::optional<unsigned int> maxPendingWriteRequests;
std::optional<unsigned int> maxPendingReadRequests;
std::optional<unsigned int> maxPendingWriteRequests;
std::function<void()> transactionFinished;
std::function<void()> terminate;

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