From 007c55e87845bc27119e2581eb5d167164df1d17 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 17 Jan 2025 15:20:07 +0100 Subject: [PATCH 1/6] Use think delay as miminum END_REQ delay When the controller accepts requests in the same clock cycle as it handles them, undeterministic simulations can occur as the outcome depends on if the new request is accepted before the controllerMethod is called or not. Therefore, a minimum delay of one clock cylce should be used to always handle request only in the next clock cycle, removing the disambiguity. --- configs/README.md | 18 +++++++++ .../DRAMSys/controller/Controller.cpp | 8 ++-- .../DRAMSys/controller/McConfig.cpp | 37 ++++--------------- src/libdramsys/DRAMSys/controller/McConfig.h | 16 ++++---- .../simulator/request/RequestIssuer.cpp | 5 --- 5 files changed, 38 insertions(+), 46 deletions(-) diff --git a/configs/README.md b/configs/README.md index 0cb516a2..37151c08 100644 --- a/configs/README.md +++ b/configs/README.md @@ -313,3 +313,21 @@ An example follows. - maximum number of active transactions per initiator (only applies to "Fifo" and "Reorder" arbiter policy) - *RefreshManagement* (boolean) - enable the sending of refresh management commands when the number of activates to one bank exceeds a certain management threshold (only supported in DDR5 and LPDDR5) +- *ArbitrationDelayFw* (unsigned int) + - number of clock cycles spent in forward arbitration to channel controllers +- *ArbitrationDelayBw* (unsigned int) + - number of clock cycles spent in backward arbitration to initiator +- *ThinkDelayFw* (unsigned int) + - minimum number of clock cycles between acceptance of a request to command issuance +- *ThinkDelayBw* (unsigned int) + - minimum number of clock cycles until response is forwarded to the arbiter +- *PhyDelayFw* (unsigned int) + - number of clock cycles between command issuance and occupation on the command/data bus +- *PhyDelayBw* (unsigned int) + - number of clock cycles between read data on the data bus and arrival in the channel controller +- *BlockingReadDelay* (unsigned int) + - constant number of clock cycles spent reading data in blocking mode + - **warning**: usage of blocking transport produces in inaccurate simulation results +- *BlockingWriteDelay* (unsigned int) + - constant number of clock cycles spent writing data in blocking mode + - **warning**: usage of blocking transport produces in inaccurate simulation results diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index 01a88faa..cd0b3ae1 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -422,7 +422,7 @@ void Controller::controllerMethod() scheduler->removeRequest(*trans); manageRequests(config.thinkDelayFw); respQueue->insertPayload(trans, - sc_time_stamp() + config.thinkDelayFw + config.phyDelayFw + + sc_time_stamp() + config.phyDelayFw + memSpec.getIntervalOnDataStrobe(command, *trans).end + config.phyDelayBw + config.thinkDelayBw); @@ -435,7 +435,7 @@ void Controller::controllerMethod() if (ranksNumberOfPayloads[rank] == 0) powerDownManagers[rank]->triggerEntry(); - sc_time fwDelay = config.thinkDelayFw + config.phyDelayFw; + sc_time fwDelay = config.phyDelayFw; tlm_phase phase = command.toPhase(); iSocket->nb_transport_fw(*trans, phase, fwDelay); } @@ -501,8 +501,8 @@ Controller::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_tim if (phase == BEGIN_REQ) { transToAcquire.payload = &trans; - transToAcquire.arrival = sc_time_stamp() + delay; - beginReqEvent.notify(delay); + transToAcquire.arrival = sc_time_stamp() + delay + config.thinkDelayFw; + beginReqEvent.notify(delay + config.thinkDelayFw); } else if (phase == END_RESP) { diff --git a/src/libdramsys/DRAMSys/controller/McConfig.cpp b/src/libdramsys/DRAMSys/controller/McConfig.cpp index 7a728569..a689efc3 100644 --- a/src/libdramsys/DRAMSys/controller/McConfig.cpp +++ b/src/libdramsys/DRAMSys/controller/McConfig.cpp @@ -57,23 +57,14 @@ McConfig::McConfig(const Config::McConfig& config, const MemSpec& memSpec) : powerDownPolicy(config.PowerDownPolicy.value_or(DEFAULT_POWER_DOWN_POLICY)), maxActiveTransactions(config.MaxActiveTransactions.value_or(DEFAULT_MAX_ACTIVE_TRANSACTIONS)), refreshManagement(config.RefreshManagement.value_or(DEFAULT_REFRESH_MANAGEMENT)), - arbitrationDelayFw(sc_core::sc_time( - config.ArbitrationDelayFw.value_or(DEFAULT_ARBITRATION_DELAY_FW_NS), sc_core::SC_NS)), - arbitrationDelayBw(sc_core::sc_time( - config.ArbitrationDelayBw.value_or(DEFAULT_ARBITRATION_DELAY_BW_NS), sc_core::SC_NS)), - thinkDelayFw( - sc_core::sc_time(config.ThinkDelayFw.value_or(DEFAULT_THINK_DELAY_FW_NS), sc_core::SC_NS)), - thinkDelayBw( - sc_core::sc_time(config.ThinkDelayBw.value_or(DEFAULT_THINK_DELAY_BW_NS), sc_core::SC_NS)), - phyDelayFw( - sc_core::sc_time(config.PhyDelayFw.value_or(DEFAULT_PHY_DELAY_FW_NS), sc_core::SC_NS)), - phyDelayBw( - sc_core::sc_time(config.PhyDelayBw.value_or(DEFAULT_PHY_DELAY_BW_NS), sc_core::SC_NS)), - blockingReadDelay(sc_core::sc_time( - config.BlockingReadDelay.value_or(DEFAULT_BLOCKING_READ_DELAY_NS), sc_core::SC_NS)), - blockingWriteDelay(sc_core::sc_time( - config.BlockingWriteDelay.value_or(DEFAULT_BLOCKING_WRITE_DELAY_NS), sc_core::SC_NS)) - + arbitrationDelayFw(config.ArbitrationDelayFw.value_or(DEFAULT_ARBITRATION_DELAY_FW) * memSpec.tCK), + arbitrationDelayBw(config.ArbitrationDelayBw.value_or(DEFAULT_ARBITRATION_DELAY_BW) * memSpec.tCK), + thinkDelayFw(config.ThinkDelayFw.value_or(DEFAULT_THINK_DELAY_FW) * memSpec.tCK), + thinkDelayBw(config.ThinkDelayBw.value_or(DEFAULT_THINK_DELAY_BW) * memSpec.tCK), + phyDelayFw(config.PhyDelayFw.value_or(DEFAULT_PHY_DELAY_FW) * memSpec.tCK), + phyDelayBw(config.PhyDelayBw.value_or(DEFAULT_PHY_DELAY_BW) * memSpec.tCK), + blockingReadDelay(config.BlockingReadDelay.value_or(DEFAULT_BLOCKING_READ_DELAY) * memSpec.tCK), + blockingWriteDelay(config.BlockingWriteDelay.value_or(DEFAULT_BLOCKING_WRITE_DELAY) * memSpec.tCK) { if (schedulerBuffer == Config::SchedulerBufferType::ReadWrite && config.RequestBufferSize.has_value()) @@ -115,18 +106,6 @@ McConfig::McConfig(const Config::McConfig& config, const MemSpec& memSpec) : if (requestBufferSizeWrite < 1) SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); - - arbitrationDelayFw = std::round(arbitrationDelayFw / memSpec.tCK) * memSpec.tCK; - arbitrationDelayBw = std::round(arbitrationDelayBw / memSpec.tCK) * memSpec.tCK; - - thinkDelayFw = std::round(thinkDelayFw / memSpec.tCK) * memSpec.tCK; - thinkDelayBw = std::round(thinkDelayBw / memSpec.tCK) * memSpec.tCK; - - phyDelayFw = std::round(phyDelayFw / memSpec.tCK) * memSpec.tCK; - phyDelayBw = std::round(phyDelayBw / memSpec.tCK) * memSpec.tCK; - - blockingReadDelay = std::round(blockingReadDelay / memSpec.tCK) * memSpec.tCK; - blockingWriteDelay = std::round(blockingWriteDelay / memSpec.tCK) * memSpec.tCK; } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/McConfig.h b/src/libdramsys/DRAMSys/controller/McConfig.h index aad546cb..5dcfef79 100644 --- a/src/libdramsys/DRAMSys/controller/McConfig.h +++ b/src/libdramsys/DRAMSys/controller/McConfig.h @@ -100,14 +100,14 @@ struct McConfig Config::PowerDownPolicyType::NoPowerDown; static constexpr unsigned int DEFAULT_MAX_ACTIVE_TRANSACTIONS = 64; static constexpr bool DEFAULT_REFRESH_MANAGEMENT = false; - static constexpr unsigned DEFAULT_ARBITRATION_DELAY_FW_NS = 0; - static constexpr unsigned DEFAULT_ARBITRATION_DELAY_BW_NS = 0; - static constexpr unsigned DEFAULT_THINK_DELAY_FW_NS = 0; - static constexpr unsigned DEFAULT_THINK_DELAY_BW_NS = 0; - static constexpr unsigned DEFAULT_PHY_DELAY_FW_NS = 0; - static constexpr unsigned DEFAULT_PHY_DELAY_BW_NS = 0; - static constexpr unsigned DEFAULT_BLOCKING_READ_DELAY_NS = 60; - static constexpr unsigned DEFAULT_BLOCKING_WRITE_DELAY_NS = 60; + static constexpr unsigned DEFAULT_ARBITRATION_DELAY_FW = 0; + static constexpr unsigned DEFAULT_ARBITRATION_DELAY_BW = 0; + static constexpr unsigned DEFAULT_THINK_DELAY_FW = 1; + static constexpr unsigned DEFAULT_THINK_DELAY_BW = 1; + static constexpr unsigned DEFAULT_PHY_DELAY_FW = 0; + static constexpr unsigned DEFAULT_PHY_DELAY_BW = 0; + static constexpr unsigned DEFAULT_BLOCKING_READ_DELAY = 60; + static constexpr unsigned DEFAULT_BLOCKING_WRITE_DELAY = 60; }; } // namespace DRAMSys diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index e36c0509..e5b825ae 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -92,11 +92,6 @@ void RequestIssuer::sendNextRequest() sendingTime -= sendingTime % clkPeriod; } - if (sendingTime == lastEndRequest) - { - sendingTime += clkPeriod; - } - delay = sendingTime - sc_core::sc_time_stamp(); iSocket->nb_transport_fw(payload, phase, delay); From 0a478dbdc5047b7c5f4b5b2194db2405cd6c150f Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 23 Jan 2025 19:40:19 +0100 Subject: [PATCH 2/6] Issue a warning if ThinkDelayFw is 0 --- src/libdramsys/DRAMSys/controller/McConfig.cpp | 3 +++ src/libdramsys/DRAMSys/controller/McConfig.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/libdramsys/DRAMSys/controller/McConfig.cpp b/src/libdramsys/DRAMSys/controller/McConfig.cpp index a689efc3..dbf82a51 100644 --- a/src/libdramsys/DRAMSys/controller/McConfig.cpp +++ b/src/libdramsys/DRAMSys/controller/McConfig.cpp @@ -106,6 +106,9 @@ McConfig::McConfig(const Config::McConfig& config, const MemSpec& memSpec) : if (requestBufferSizeWrite < 1) SC_REPORT_FATAL("Configuration", "Minimum request buffer size is 1!"); + + if (thinkDelayFw == sc_core::SC_ZERO_TIME) + SC_REPORT_WARNING("Configuration", "ThinkDelayFw should at least be 1!"); } } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/McConfig.h b/src/libdramsys/DRAMSys/controller/McConfig.h index 5dcfef79..1b120c45 100644 --- a/src/libdramsys/DRAMSys/controller/McConfig.h +++ b/src/libdramsys/DRAMSys/controller/McConfig.h @@ -103,7 +103,7 @@ struct McConfig static constexpr unsigned DEFAULT_ARBITRATION_DELAY_FW = 0; static constexpr unsigned DEFAULT_ARBITRATION_DELAY_BW = 0; static constexpr unsigned DEFAULT_THINK_DELAY_FW = 1; - static constexpr unsigned DEFAULT_THINK_DELAY_BW = 1; + static constexpr unsigned DEFAULT_THINK_DELAY_BW = 0; static constexpr unsigned DEFAULT_PHY_DELAY_FW = 0; static constexpr unsigned DEFAULT_PHY_DELAY_BW = 0; static constexpr unsigned DEFAULT_BLOCKING_READ_DELAY = 60; From 1225f6b044161f97bf1bac520884f71a68b2730e Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Thu, 23 Jan 2025 19:45:57 +0100 Subject: [PATCH 3/6] Fix tests after ThinkDelayFw --- .../DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb | 4 ++-- .../DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb | 4 ++-- .../DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb | 4 ++-- .../DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb | 4 ++-- .../HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb | 4 ++-- .../HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb | 4 ++-- .../HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb | 2 +- .../LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb | 4 ++-- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb b/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb index e0ee5426..34af54f0 100644 --- a/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb +++ b/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2eadd8204bd90b18e7f5a12a71382f9d0cfbeaf33066961a7cb89f388d51b53c -size 135168 +oid sha256:a70796cd5737f5196f00f90aea6650166447f710791dfb502908ebc81e50c9b3 +size 139264 diff --git a/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb b/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb index 95463ec1..00999871 100644 --- a/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb +++ b/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:fa0b42d8faac2a076fbc434fdc47b5f722e6a640ee8b3ed45b8d4976c7debddd -size 5025792 +oid sha256:93a341b43bd3cc86b92fdb752a442c5e377e533072976604169ccedf8b3ba27e +size 5050368 diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb index d7c96b81..672822b6 100644 --- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb +++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0e8a22954bf100e69ceb7d9454d61a6c575c67f087b84658d05d5b394d94b9c6 -size 6045696 +oid sha256:aa41c4bc86b3e93ed4b425e3e4ee57eadda073b1fdc1c7937f592fa5807119b5 +size 6094848 diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb index 091bea04..84dc9006 100644 --- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb +++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a77f157b1929b8e4f5302e68b06ef468cbb2edf32e6c57579dfceb777c6d528e -size 94208 +oid sha256:35383e4cf7774769c957730022c6455307b99c9d89e0c7575735f0a61f187f70 +size 86016 diff --git a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb index 606e62e0..5a1cd5af 100644 --- a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb +++ b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:951ff2fb9a982cb421748222c8fffcfd1e1856b831ee17ccdb30ef93f1ee309c -size 671744 +oid sha256:3b459e5ccff77d82f0322662ddf6d9755c361d4a7d5d859118c1b54cdaac696a +size 675840 diff --git a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb index dbc252d2..20500403 100644 --- a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb +++ b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c7465ec3484b87ecd8a75491b34e86f4e9cf716fad1f12fe59a1099572c8c586 -size 675840 +oid sha256:9df69fa35ff2d16496b88581d9b5e102fcda9f2cd6da4f41343347cdfca23a4b +size 684032 diff --git a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb index be988a77..9430840f 100644 --- a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb +++ b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:1254a897c32283003a030de279f0b65c464fd026a9d9989354c52bdc29c84dbb +oid sha256:f16b3b2af3376497e605f92f1a24b5e3aeda1426eb418edc3180f4b08f4ca6dc size 1376256 diff --git a/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb b/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb index b2c11196..476a5dcd 100644 --- a/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb +++ b/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:64acfb8c773c65c91a3bcad996419de80cff7780378a663c9ead2e53da0030c2 -size 2826240 +oid sha256:2ccf95f3c3ef976e392239c189fe0e992a0eaac90783918f29230e03af0fd4b8 +size 2834432 From ba94d9fd84efe0396160aac93cecd6e4f157a49e Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 24 Jan 2025 14:42:48 +0100 Subject: [PATCH 4/6] Have a one cycle END_RESP delay in the standard initiator --- src/simulator/simulator/request/RequestIssuer.cpp | 2 +- .../DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb | 2 +- .../DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb | 2 +- .../DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb | 4 ++-- .../DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb | 2 +- .../HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb | 2 +- .../HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb | 2 +- .../HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb | 2 +- .../LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb | 4 ++-- .../LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb | 3 --- .../LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb | 3 +++ 11 files changed, 14 insertions(+), 14 deletions(-) delete mode 100644 tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb create mode 100644 tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index e5b825ae..a91f138e 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -131,7 +131,7 @@ void RequestIssuer::peqCallback(tlm::tlm_generic_payload& payload, const tlm::tl else if (phase == tlm::BEGIN_RESP) { tlm::tlm_phase nextPhase = tlm::END_RESP; - sc_core::sc_time delay = sc_core::SC_ZERO_TIME; + sc_core::sc_time delay = clkPeriod; iSocket->nb_transport_fw(payload, nextPhase, delay); payload.release(); diff --git a/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb b/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb index 34af54f0..88d7a543 100644 --- a/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb +++ b/tests/tests_regression/DDR3/expected/DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a70796cd5737f5196f00f90aea6650166447f710791dfb502908ebc81e50c9b3 +oid sha256:ce0fe36061b63a23c0323a2748f1da657bedda18bbf27e2a34edb0fad4c0fdb8 size 139264 diff --git a/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb b/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb index 00999871..f78440a3 100644 --- a/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb +++ b/tests/tests_regression/DDR4/expected/DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:93a341b43bd3cc86b92fdb752a442c5e377e533072976604169ccedf8b3ba27e +oid sha256:df2c6750bfad509dc4746a876ebc090eae5a4006df05b9d8ccb5aeac673830ac size 5050368 diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb index 672822b6..422b368a 100644 --- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb +++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:aa41c4bc86b3e93ed4b425e3e4ee57eadda073b1fdc1c7937f592fa5807119b5 -size 6094848 +oid sha256:a8b0a34309e16c0e2b5ef35f4c07e1e427c4803bf9eb31789f3b0f9569fd211e +size 6082560 diff --git a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb index 84dc9006..351f93b0 100644 --- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb +++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:35383e4cf7774769c957730022c6455307b99c9d89e0c7575735f0a61f187f70 +oid sha256:cd92a1a680c0d9e38e199b5730f8f6ccacd6e2371adb5af58e9ea2ab70f4d647 size 86016 diff --git a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb index 5a1cd5af..cbf342c2 100644 --- a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb +++ b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3b459e5ccff77d82f0322662ddf6d9755c361d4a7d5d859118c1b54cdaac696a +oid sha256:c07d0788e550884138f84803c0baf0c634a61ce225698eaedb39f9e828f62c65 size 675840 diff --git a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb index 20500403..1bea7de6 100644 --- a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb +++ b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9df69fa35ff2d16496b88581d9b5e102fcda9f2cd6da4f41343347cdfca23a4b +oid sha256:db5321193521e8eb75654a545ba1155b7c707ee993ab67ae96b2639e278fc9d7 size 684032 diff --git a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb index 9430840f..2b9be0e0 100644 --- a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb +++ b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:f16b3b2af3376497e605f92f1a24b5e3aeda1426eb418edc3180f4b08f4ca6dc +oid sha256:a024bffa4f7c2653b0dae899cbef84e8e7e6af7d0fe72e6bd14c45fe627c6cd7 size 1376256 diff --git a/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb b/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb index 476a5dcd..756b5039 100644 --- a/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb +++ b/tests/tests_regression/LPDDR4/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:2ccf95f3c3ef976e392239c189fe0e992a0eaac90783918f29230e03af0fd4b8 -size 2834432 +oid sha256:a4921b32bbb3f0ff22c462d8a6c768fcbeca0b6e05b6c00f79efbccb364acde4 +size 2863104 diff --git a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb deleted file mode 100644 index b2c11196..00000000 --- a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:64acfb8c773c65c91a3bcad996419de80cff7780378a663c9ead2e53da0030c2 -size 2826240 diff --git a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb new file mode 100644 index 00000000..41e0c57c --- /dev/null +++ b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_example_ch0.tdb @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0224d8e5daa7bd509951a7cf61dbac80bb9747a4773d30da64f08b5a31c7de3a +size 3727360 From 581794b970978883eef432383144296fed82b07b Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 24 Jan 2025 14:56:53 +0100 Subject: [PATCH 5/6] Allow responses to be sent back-to-back --- src/libdramsys/DRAMSys/controller/Controller.cpp | 14 ++------------ .../expected/DRAMSys_hbm3-example_hbm3_ch0.tdb | 2 +- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/src/libdramsys/DRAMSys/controller/Controller.cpp b/src/libdramsys/DRAMSys/controller/Controller.cpp index cd0b3ae1..19a0ff8c 100644 --- a/src/libdramsys/DRAMSys/controller/Controller.cpp +++ b/src/libdramsys/DRAMSys/controller/Controller.cpp @@ -659,12 +659,7 @@ void Controller::manageResponses() { transToRelease.payload = &parentTrans; tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay; - if (transToRelease.arrival == - sc_time_stamp()) // last payload was released in this cycle - bwDelay = memSpec.tCK; - else - bwDelay = SC_ZERO_TIME; + sc_time bwDelay = SC_ZERO_TIME; sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); transToRelease.arrival = scMaxTime; @@ -680,12 +675,7 @@ void Controller::manageResponses() { transToRelease.payload = nextTransInRespQueue; tlm_phase bwPhase = BEGIN_RESP; - sc_time bwDelay; - if (transToRelease.arrival == - sc_time_stamp()) // last payload was released in this cycle - bwDelay = memSpec.tCK; - else - bwDelay = SC_ZERO_TIME; + sc_time bwDelay = SC_ZERO_TIME; sendToFrontend(*transToRelease.payload, bwPhase, bwDelay); transToRelease.arrival = scMaxTime; diff --git a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb index 2b9be0e0..379cce48 100644 --- a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb +++ b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a024bffa4f7c2653b0dae899cbef84e8e7e6af7d0fe72e6bd14c45fe627c6cd7 +oid sha256:caa32221ae565b3c7d3d61025dadb0a28c7644a323f2b2ad278eac49cf92e528 size 1376256 From e57ce9cc8662b2d26ea2cb2ca456d102f6710728 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Fri, 24 Jan 2025 15:55:40 +0100 Subject: [PATCH 6/6] Use controller clock as interface clock in initiators --- src/simulator/simulator/SimpleInitiator.h | 4 ++-- src/simulator/simulator/Simulator.cpp | 8 +++++--- .../simulator/generator/TrafficGenerator.cpp | 13 +++++++++---- .../simulator/generator/TrafficGenerator.h | 11 +++++++---- src/simulator/simulator/request/RequestIssuer.cpp | 13 +++---------- src/simulator/simulator/request/RequestIssuer.h | 8 ++++---- 6 files changed, 30 insertions(+), 27 deletions(-) diff --git a/src/simulator/simulator/SimpleInitiator.h b/src/simulator/simulator/SimpleInitiator.h index 410588d4..8c134b1a 100644 --- a/src/simulator/simulator/SimpleInitiator.h +++ b/src/simulator/simulator/SimpleInitiator.h @@ -43,7 +43,7 @@ template class SimpleInitiator : public Initiator public: SimpleInitiator(sc_core::sc_module_name const& name, MemoryManager& memoryManager, - unsigned int clkMhz, + sc_core::sc_time interfaceClk, std::optional maxPendingReadRequests, std::optional maxPendingWriteRequests, std::function transactionFinished, @@ -53,7 +53,7 @@ public: issuer( name, memoryManager, - clkMhz, + interfaceClk, maxPendingReadRequests, maxPendingWriteRequests, [this] { return this->producer.nextRequest(); }, diff --git a/src/simulator/simulator/Simulator.cpp b/src/simulator/simulator/Simulator.cpp index 24443a64..09b87ff0 100644 --- a/src/simulator/simulator/Simulator.cpp +++ b/src/simulator/simulator/Simulator.cpp @@ -84,6 +84,7 @@ std::unique_ptr Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator) { uint64_t memorySize = dramSys->getMemSpec().getSimMemSizeInBytes(); + sc_core::sc_time interfaceClk = dramSys->getMemSpec().tCK; unsigned int defaultDataLength = dramSys->getMemSpec().defaultBytesPerBurst; return std::visit( @@ -94,9 +95,10 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator) std::is_same_v) { return std::make_unique(config, - memoryManager, + interfaceClk, memorySize, defaultDataLength, + memoryManager, finishTransaction, terminateInitiator); } @@ -126,7 +128,7 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator) return std::make_unique>(config.name.c_str(), memoryManager, - config.clkMhz, + interfaceClk, std::nullopt, std::nullopt, finishTransaction, @@ -139,7 +141,7 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator) return std::make_unique>(config.name.c_str(), memoryManager, - config.clkMhz, + interfaceClk, 1, 1, finishTransaction, diff --git a/src/simulator/simulator/generator/TrafficGenerator.cpp b/src/simulator/simulator/generator/TrafficGenerator.cpp index b3318040..d4928a23 100644 --- a/src/simulator/simulator/generator/TrafficGenerator.cpp +++ b/src/simulator/simulator/generator/TrafficGenerator.cpp @@ -35,10 +35,14 @@ #include "TrafficGenerator.h" +#include "RandomProducer.h" +#include "SequentialProducer.h" + TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const& config, - MemoryManager& memoryManager, + sc_core::sc_time interfaceClk, uint64_t memorySize, unsigned int defaultDataLength, + MemoryManager& memoryManager, std::function transactionFinished, std::function terminateInitiator) : stateTransistions(config.transitions), @@ -46,7 +50,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine issuer( config.name.c_str(), memoryManager, - config.clkMhz, + interfaceClk, config.maxPendingReadRequests, config.maxPendingWriteRequests, [this] { return nextRequest(); }, @@ -107,16 +111,17 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine } TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const& config, - MemoryManager& memoryManager, + sc_core::sc_time interfaceClk, uint64_t memorySize, unsigned int defaultDataLength, + MemoryManager& memoryManager, std::function transactionFinished, std::function terminateInitiator) : generatorPeriod(sc_core::sc_time(1.0 / static_cast(config.clkMhz), sc_core::SC_US)), issuer( config.name.c_str(), memoryManager, - config.clkMhz, + interfaceClk, config.maxPendingReadRequests, config.maxPendingWriteRequests, [this] { return nextRequest(); }, diff --git a/src/simulator/simulator/generator/TrafficGenerator.h b/src/simulator/simulator/generator/TrafficGenerator.h index 8892494c..335abc2d 100644 --- a/src/simulator/simulator/generator/TrafficGenerator.h +++ b/src/simulator/simulator/generator/TrafficGenerator.h @@ -35,28 +35,31 @@ #pragma once -#include "RandomProducer.h" -#include "SequentialProducer.h" #include "simulator/Initiator.h" #include "simulator/MemoryManager.h" #include "simulator/request/RequestIssuer.h" #include +#include + +class RequestProducer; class TrafficGenerator : public Initiator { public: TrafficGenerator(DRAMSys::Config::TrafficGenerator const& config, - MemoryManager& memoryManager, + sc_core::sc_time interfaceClk, uint64_t memorySize, unsigned int defaultDataLength, + MemoryManager& memoryManager, std::function transactionFinished, std::function terminateInitiator); TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine const& config, - MemoryManager& memoryManager, + sc_core::sc_time interfaceClk, uint64_t memorySize, unsigned int defaultDataLength, + MemoryManager& memoryManager, std::function transactionFinished, std::function terminateInitiator); diff --git a/src/simulator/simulator/request/RequestIssuer.cpp b/src/simulator/simulator/request/RequestIssuer.cpp index a91f138e..d1d46f45 100644 --- a/src/simulator/simulator/request/RequestIssuer.cpp +++ b/src/simulator/simulator/request/RequestIssuer.cpp @@ -37,7 +37,7 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const& name, MemoryManager& memoryManager, - unsigned int clkMhz, + sc_core::sc_time interfaceClk, std::optional maxPendingReadRequests, std::optional maxPendingWriteRequests, std::function nextRequest, @@ -46,7 +46,7 @@ RequestIssuer::RequestIssuer(sc_core::sc_module_name const& name, sc_module(name), payloadEventQueue(this, &RequestIssuer::peqCallback), memoryManager(memoryManager), - clkPeriod(sc_core::sc_time(1.0 / static_cast(clkMhz), sc_core::SC_US)), + interfaceClk(interfaceClk), maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests), transactionFinished(std::move(transactionFinished)), @@ -85,13 +85,6 @@ void RequestIssuer::sendNextRequest() sc_core::sc_time sendingTime = sc_core::sc_time_stamp() + delay; - bool needsOffset = (sendingTime % clkPeriod) != sc_core::SC_ZERO_TIME; - if (needsOffset) - { - sendingTime += clkPeriod; - sendingTime -= sendingTime % clkPeriod; - } - delay = sendingTime - sc_core::sc_time_stamp(); iSocket->nb_transport_fw(payload, phase, delay); @@ -131,7 +124,7 @@ void RequestIssuer::peqCallback(tlm::tlm_generic_payload& payload, const tlm::tl else if (phase == tlm::BEGIN_RESP) { tlm::tlm_phase nextPhase = tlm::END_RESP; - sc_core::sc_time delay = clkPeriod; + sc_core::sc_time delay = interfaceClk; iSocket->nb_transport_fw(payload, nextPhase, delay); payload.release(); diff --git a/src/simulator/simulator/request/RequestIssuer.h b/src/simulator/simulator/request/RequestIssuer.h index 2d21c38b..1c86b70d 100644 --- a/src/simulator/simulator/request/RequestIssuer.h +++ b/src/simulator/simulator/request/RequestIssuer.h @@ -52,7 +52,7 @@ public: RequestIssuer(sc_core::sc_module_name const& name, MemoryManager& memoryManager, - unsigned int clkMhz, + sc_core::sc_time interfaceClk, std::optional maxPendingReadRequests, std::optional maxPendingWriteRequests, std::function nextRequest, @@ -64,7 +64,7 @@ private: tlm_utils::peq_with_cb_and_phase payloadEventQueue; MemoryManager& memoryManager; - const sc_core::sc_time clkPeriod; + sc_core::sc_time interfaceClk; bool transactionPostponed = false; bool finished = false; @@ -75,8 +75,8 @@ private: unsigned int pendingReadRequests = 0; unsigned int pendingWriteRequests = 0; - const std::optional maxPendingReadRequests; - const std::optional maxPendingWriteRequests; + std::optional maxPendingReadRequests; + std::optional maxPendingWriteRequests; std::function transactionFinished; std::function terminate;