derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,159 Commits 1 Branch 0 Tags
8ba08e9bd4de46be5d35bfa2668b4a30e0d3d5bf
Commit Graph

164 Commits

Author SHA1 Message Date
Matthias Jung
8ba08e9bd4 Ability to specify a different resource folder 2018-11-08 23:28:19 +01:00
Éder F. Zulian
3bd9082650 doc update 2018-11-08 13:18:53 +01:00
Éder F. Zulian
8bafb07d24 Fixes - repository URL and repository updated 
github --> gitlab
dram.vp.system --> dram.sys
 2018-10-30 16:36:06 +01:00
Matthias Jung
3655ceb4e4 Update README.md w.r.t. CI infos 2018-10-24 23:00:42 +02:00
Éder F. Zulian
210d38f938 Env var for selecting libpython version 2018-09-26 13:37:06 +02:00
Éder F. Zulian
dede0bed69 small fix 2018-09-07 13:28:10 +02:00
Éder F. Zulian
f27eced780 DRAMSys_gem5 - numumber of transactors from config 
DRAMSys - new config UseMalloc (default is mmap())
 2018-09-07 13:21:58 +02:00
Éder F. Zulian
53f7b5e162 Script for running DRAMSys_gem5 
Right now SE mode only.
 2018-09-07 08:53:11 +02:00
Éder F. Zulian
a00cb68d01 Elastic traces scripts and gem5 configs fixed. 
Documentation improved.
 2018-09-03 17:23:06 +02:00
Éder F. Zulian
8b0c74bbd6 doc improved 2018-08-30 13:46:39 +02:00
Éder F. Zulian
e8bdd28bc6 doc improved 2018-08-30 13:40:56 +02:00
Éder F. Zulian
332c0d925c doc improved 2018-08-30 13:31:49 +02:00
Éder F. Zulian
b0343beac1 DRAMSys_gem5 functional examples, essential files and doc 
This commit intends to provide functional examples and doc.
 2018-08-30 13:15:54 +02:00
Éder F. Zulian
0ae7eb842e Doc improved 2018-08-29 14:25:18 +02:00
Éder F. Zulian
4d83bec990 doc improved 2018-08-28 14:21:47 +02:00
Éder F. Zulian
ff3f5ac2f4 Doc improved 2018-08-28 12:00:15 +02:00
Éder F. Zulian
6436087b2e Doc improved 2018-08-28 11:28:41 +02:00
Éder F. Zulian
4c6752cf6a Doc improved + path to find gem5 library 2018-08-27 14:57:01 +02:00
Éder F. Zulian
634bfd0312 DRAMSylva - support to list of JSON config files 2018-07-24 12:23:00 +02:00
Éder F. Zulian
ef3e88057a DRAMSylva - support to compresed traces 2018-07-23 14:26:13 +02:00
Éder F. Zulian
d8ec15436f doc improved 2018-07-20 09:56:09 +02:00
Éder F. Zulian
ed5b0c30fe doc improved 2018-07-20 09:42:04 +02:00
Éder F. Zulian
82d4c164f0 DRAMSylva refactored 
DRAMSylva (or parts of it) will be possibly used in auto tests.
 2018-07-19 13:32:55 +02:00
Éder F. Zulian
d0c889da06 Doc updated 2018-07-17 16:40:27 +02:00
Éder F. Zulian
d0e0835387 doc updated 2018-07-13 15:57:34 +02:00
Éder F. Zulian
a48b1a2c51 doc updated 2018-07-12 18:24:27 +02:00
Éder F. Zulian
389d947621 doc updated 2018-07-12 18:19:57 +02:00
Éder F. Zulian
19ac04774b DRAMSylva - Using json for configs 2018-07-12 11:29:03 +02:00
Éder F. Zulian
f42f95f217 Doc improved 2018-07-12 09:26:01 +02:00
Éder F. Zulian
c2a0e9ddd1 Doc improved 2018-07-12 09:22:09 +02:00
Éder F. Zulian
a3ce6f3d26 Doc improved 2018-07-12 08:30:51 +02:00
Éder F. Zulian
6c712fc941 ControllerCoreRGRNumARIntREFI --> ControllerCoreRefNumARCmdsIntREFI 
Documentation updated.
 2018-07-10 16:02:04 +02:00
Éder F. Zulian
c6e66305c1 Standard nomenclature for refresh related configs. 
ControllerCoreRef* for refresh general configs.
ControllerCoreRGR* for RGR specific configs.
 2018-07-10 09:44:48 +02:00
Éder F. Zulian
7ca6396766 Doc improved 2018-07-05 13:12:39 +02:00
Éder F. Zulian
d579060e8e Doc improved 2018-07-05 08:19:31 +02:00
Éder F. Zulian
2e307d00e8 Doc improved 2018-07-05 08:09:36 +02:00
Éder F. Zulian
6c5c49179a Commit of the following: 
Changed stlPlayer to template class.
Integrated the relative stl player.
 2018-07-03 15:03:36 +02:00
Éder F. Zulian
0ace967a67 Refresh modes 1X, 2X and 4X - tRFC 2018-07-03 11:24:06 +02:00
Éder F. Zulian
00e57139f0 indentation 2018-07-02 12:15:56 +02:00
Éder F. Zulian
88f604b7bf Doc improved 2018-07-02 12:11:14 +02:00
Éder F. Zulian
8f9751f30f Refresh modes 1X, 2X and 4X. 2018-07-02 07:50:28 +02:00
Éder F. Zulian
0a992391d2 Following changes: 
Show rgr related config during initialization.
ORGR in traceAnalyzer.
Submodule drampower set properly (point to rgr branch).
New config for row increment (selective ref.).
Specific simulations NO REF. and AR with close page policy.
Simulation files ddr4 1, 2, 4 x mode open, close page policy, no ref, ar, rgr, orgr.
New config for number of auto-ref. cmds in 64 ms.
New traces for ddr4.
New spec for dd4 16Gb after Christian's corrections.
Initial offset for bankwise logic (if zeroed, for research).
ORGR/RGR.
Flex. ORGR/RGR.
Bankwise flex. refresh.
Small schanges.
RGR flex test files.
Doc updated.
 2018-06-28 14:35:14 +02:00
Éder F. Zulian
024bad03bb fix 2018-06-22 10:14:23 +02:00
Éder F. Zulian
5342c07976 scripts and doc updated 2018-06-20 12:45:08 +02:00
Matthias Jung
412630122c Added Information about Windows Compiling 2018-06-08 14:30:53 +02:00
Éder F. Zulian
b59dd058ca Trace list made optional in DRAMSylva 2018-06-04 18:38:12 +02:00
Éder F. Zulian
8d6b605419 Doc updated 2018-06-04 17:03:34 +02:00
Éder F. Zulian
9945db4f4b doc updated 2018-05-30 10:12:40 +02:00
Éder F. Zulian
bf6558a231 doc updated 2018-05-29 19:17:19 +02:00
Éder F. Zulian
5a6aa137fa Reference to coding-style document on README.md 2018-05-28 17:48:25 +02:00