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DRAMSys_gem5 functional examples, essential files and doc

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This commit intends to provide functional examples and doc.
This commit is contained in:
Éder F. Zulian
2018-08-30 12:57:59 +02:00
parent 0ae7eb842e
commit b0343beac1
13 changed files with 3163 additions and 0 deletions
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@@ -20,3 +20,4 @@ DRAMSys/analyzer/scripts/__pycache__/
*.pyc
*.autosave
*__pycache__*
DRAMSys/gem5/boot_linux/linux-aarch32-ael.img

247
DRAMSys/docs/images/gem5_se_mode_arch.svg Normal file
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<text text-anchor="middle" x="449" y="-439.8" font-family="Arial" font-size="14.00" fill="#000000">master</text>
</g>
<!-- system_l2_cpu_side -->
<g id="node8" class="node"><title>system_l2_cpu_side</title>
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<text text-anchor="middle" x="403" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_tol2bus_master&#45;&gt;system_l2_cpu_side -->
<g id="edge3" class="edge"><title>system_tol2bus_master&#45;&gt;system_l2_cpu_side</title>
<path fill="none" stroke="black" d="M442.892,-425.37C435.124,-403.588 421.63,-365.744 412.51,-340.17"/>
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</g>
<!-- system_tol2bus_slave -->
<g id="node6" class="node"><title>system_tol2bus_slave</title>
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<text text-anchor="middle" x="374" y="-439.8" font-family="Arial" font-size="14.00" fill="#000000">slave</text>
</g>
<!-- system_l2_mem_side -->
<g id="node7" class="node"><title>system_l2_mem_side</title>
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<text text-anchor="middle" x="500" y="-308.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_l2_mem_side&#45;&gt;system_membus_slave -->
<g id="edge4" class="edge"><title>system_l2_mem_side&#45;&gt;system_membus_slave</title>
<path fill="none" stroke="black" d="M466.462,-294.374C430.995,-276.175 379.636,-249.529 376,-246 365.309,-235.623 356.845,-221.384 350.817,-209.019"/>
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</g>
<!-- system_cpu_icache_port -->
<g id="node9" class="node"><title>system_cpu_icache_port</title>
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<text text-anchor="middle" x="192" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">icache_port</text>
</g>
<!-- system_cpu_icache_cpu_side -->
<g id="node14" class="node"><title>system_cpu_icache_cpu_side</title>
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<text text-anchor="middle" x="277" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu_icache_port&#45;&gt;system_cpu_icache_cpu_side -->
<g id="edge5" class="edge"><title>system_cpu_icache_port&#45;&gt;system_cpu_icache_cpu_side</title>
<path fill="none" stroke="black" d="M203.287,-687.37C217.83,-665.299 243.24,-626.736 260.093,-601.158"/>
<polygon fill="black" stroke="black" points="263.086,-602.977 265.666,-592.701 257.241,-599.126 263.086,-602.977"/>
</g>
<!-- system_cpu_dcache_port -->
<g id="node10" class="node"><title>system_cpu_dcache_port</title>
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<text text-anchor="middle" x="80" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">dcache_port</text>
</g>
<!-- system_cpu_dcache_cpu_side -->
<g id="node16" class="node"><title>system_cpu_dcache_cpu_side</title>
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<text text-anchor="middle" x="77" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">cpu_side</text>
</g>
<!-- system_cpu_dcache_port&#45;&gt;system_cpu_dcache_cpu_side -->
<g id="edge6" class="edge"><title>system_cpu_dcache_port&#45;&gt;system_cpu_dcache_cpu_side</title>
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<polygon fill="black" stroke="black" points="81.1317,-602.617 77.4,-592.701 74.1336,-602.78 81.1317,-602.617"/>
</g>
<!-- system_cpu_dtb_walker_port -->
<g id="node11" class="node"><title>system_cpu_dtb_walker_port</title>
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<text text-anchor="middle" x="347" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_cpu_dtb_walker_port&#45;&gt;system_tol2bus_slave -->
<g id="edge7" class="edge"><title>system_cpu_dtb_walker_port&#45;&gt;system_tol2bus_slave</title>
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</g>
<!-- system_cpu_itb_walker_port -->
<g id="node12" class="node"><title>system_cpu_itb_walker_port</title>
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<text text-anchor="middle" x="455" y="-701.8" font-family="Arial" font-size="14.00" fill="#000000">port</text>
</g>
<!-- system_cpu_itb_walker_port&#45;&gt;system_tol2bus_slave -->
<g id="edge8" class="edge"><title>system_cpu_itb_walker_port&#45;&gt;system_tol2bus_slave</title>
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</g>
<!-- system_cpu_icache_mem_side -->
<g id="node13" class="node"><title>system_cpu_icache_mem_side</title>
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<text text-anchor="middle" x="374" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_cpu_icache_mem_side&#45;&gt;system_tol2bus_slave -->
<g id="edge9" class="edge"><title>system_cpu_icache_mem_side&#45;&gt;system_tol2bus_slave</title>
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</g>
<!-- system_cpu_dcache_mem_side -->
<g id="node15" class="node"><title>system_cpu_dcache_mem_side</title>
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<text text-anchor="middle" x="174" y="-570.8" font-family="Arial" font-size="14.00" fill="#000000">mem_side</text>
</g>
<!-- system_cpu_dcache_mem_side&#45;&gt;system_tol2bus_slave -->
<g id="edge10" class="edge"><title>system_cpu_dcache_mem_side&#45;&gt;system_tol2bus_slave</title>
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</g>
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</svg>
Side by Side

After

Width:  |  Height:  |  Size: 28 KiB

BIN
DRAMSys/gem5/boot_linux/boot_emm.arm Normal file
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BIN
DRAMSys/gem5/boot_linux/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb Normal file
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Binary file not shown.

1636
DRAMSys/gem5/configs/boot_linux.ini Normal file
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553
DRAMSys/gem5/configs/bubblesort.ini Normal file
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@@ -0,0 +1,553 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory l2 membus physmem tol2bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=65536
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.tol2bus.slave[1]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=65536
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[3]
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.tol2bus.slave[0]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[2]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/Bubblesort
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/Bubblesort
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.l2]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.l2.replacement_policy
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.l2.tags
tgts_per_mshr=12
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.tol2bus.master[0]
mem_side=system.membus.slave[1]
[system.l2.replacement_policy]
type=LRURP
eventq_index=0
[system.l2.tags]
type=BaseSetAssoc
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.l2.replacement_policy
sequential_access=false
size=2097152
tag_latency=20
warmup_percentage=0
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.external_memory.port
slave=system.system_port system.l2.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tol2bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
point_of_unification=true
power_model=
response_latency=1
snoop_filter=system.tol2bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.tol2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

553
DRAMSys/gem5/configs/hello.ini Normal file
View File

@@ -0,0 +1,553 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory l2 membus physmem tol2bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=65536
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.tol2bus.slave[1]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=65536
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[3]
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.tol2bus.slave[0]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[2]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.l2]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.l2.replacement_policy
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.l2.tags
tgts_per_mshr=12
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.tol2bus.master[0]
mem_side=system.membus.slave[1]
[system.l2.replacement_policy]
type=LRURP
eventq_index=0
[system.l2.tags]
type=BaseSetAssoc
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.l2.replacement_policy
sequential_access=false
size=2097152
tag_latency=20
warmup_percentage=0
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.external_memory.port
slave=system.system_port system.l2.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tol2bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
point_of_unification=true
power_model=
response_latency=1
snoop_filter=system.tol2bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.tol2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

BIN
DRAMSys/gem5/gem5_se/hello Executable file
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Binary file not shown.

28
DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.xml Normal file
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<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="Store" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
-->
<AddressOffset value = "2147483648" />
</simconfig>

28
DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.xml Normal file
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<simconfig>
<SimulationName value="ddr3" />
<Debug value="0" />
<DatabaseRecording value="1" />
<PowerAnalysis value="1" />
<EnableWindowing value = "1" />
<WindowSize value="1000" />
<ThermalSimulation value="0"/>
<SimulationProgressBar value="1"/>
<NumberOfMemChannels value="1"/>
<NumberOfDevicesOnDIMM value = "8" />
<CheckTLM2Protocol value = "0" />
<AddressOffset value = "0" />
<ECCControllerMode value = "Disabled" />
<ErrorChipSeed value="42" />
<ErrorCSVFile value="" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="Store" />
<!-- Gem5 Related Configuration:
In the memory controller file the storage mode should be set to Store
E.g. the DRAM is located at 0x80000000 for gem5
<AddressOffset value = "2147483648" />
-->
</simconfig>

25
DRAMSys/library/resources/simulations/ddr3-boot-linux.xml Normal file
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@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3_boot_linux.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

25
DRAMSys/library/resources/simulations/ddr3-gem5-se.xml Normal file
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@@ -0,0 +1,25 @@
<simulation>
<!-- Simulation file identifier -->
<simulationid id="ddr3-example"></simulationid>
<!-- Configuration for the DRAMSys Simulator -->
<simconfig src="ddr3_gem5_se.xml" />
<!-- Temperature Simulator Configuration -->
<thermalconfig src="config.xml" />
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--
The following trace setup is only used in standalone mode.
In library mode e.g. in Platform Architect the trace setup is ignored.
-->
<tracesetup>
<!--
This device mimics an image processing application
running on an FPGA with 200 Mhz.
-->
<device clkMhz="200">ddr3_example.stl</device>
</tracesetup>
</simulation>

67
README.md
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@@ -1547,6 +1547,50 @@ Lets run the simulation for some seconds and then stop the simulation with
**CTRL-C**. Observe the output of the simulation in the trace analyzer. The trace
database file is stored in the gem5 directory in the building directory.
### Gem5 SE mode and DRAMSys
All essential files for some functional examples are provided.
Execute a hello world application:
``` bash
./DRAMSys_gem5 /home/eder/repos/dram.vp.system/DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/configs/hello.ini
```
A **Hello world!** message should be printed to the standard output.
Execute a bubble sort application:
``` bash
./DRAMSys_gem5 /home/eder/repos/dram.vp.system/DRAMSys/library/resources/simulations/ddr3-gem5-se.xml ../../DRAMSys/gem5/configs/bubblesort.ini
```
Wait some minutes for the bubble sort application to finish.
The hello application binary was copied from gem5 repository. The bubble sort application was obtained with [gem5.TnT](https://github.com/tukl-msd/gem5.TnT).
Command template for generating **.ini** configuration files follows:
``` bash
build/ARM/gem5.opt configs/example/se.py -c <application> --mem-size=512MB --mem-channels=1 --caches --l2cache --mem-type=SimpleMemory --cpu-type=TimingSimpleCPU --num-cpu=1 --tlm-memory=transactor
```
An overview of the architcture being simulated is presented below:
![arch](DRAMSys/docs/images/gem5_se_mode_arch.png)
Note: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is
direct connected as external tlm slave.
Note: workaround in se.py required:
```
...
if options.tlm_memory:
system.physmem = SimpleMemory()
MemConfig.config_mem(options, system)
...
```
### Boot Linux with gem5 and DRAMSys
The procedure is very similar to the traffic generator example above.
@@ -1607,6 +1651,29 @@ Then start DRAMSys_gem5 with the following command:
For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp
All essential files for a functional example are provided.
Unzip the disk image:
``` bash
tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/boot_linux/
```
Execute the example:
``` bash
./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.xml ../../DRAMSys/gem5/configs/boot_linux.ini
```
Open a new terminal and connect to gem5:
``` bash
telnet localhost 3456
```
Wait some minutes for the Linux boot process to complete then login. Username is **root** no password required.
### DRAMSys with gem5 Elastic Traces
For understanding elastic traces and their generation, study the [gem5 wiki](http://gem5.org/TraceCPU) and the paper [13].