This commit is contained in:
Éder F. Zulian
2018-06-22 10:14:23 +02:00
parent 5342c07976
commit 024bad03bb

View File

@@ -617,7 +617,7 @@ Below, the sub-configurations are listed and explained.
- "bank_bits": Number of the addres bits which are connected to a bank bit
- "row_bits": Number of the addres bits which are connected to a row bit
```json
``` json
{
"Config": {
"numberOfBankBits": 3,
@@ -665,32 +665,30 @@ Below, the sub-configurations are listed and explained.
}
```
- **Memory Configuration**
The content of [fifo.xml](DRAMSys/library/resources/configs/memconfigs/fifo.xml) is
- **Memory Controller Configuration**
The content of [fifo.xml](DRAMSys/library/resources/configs/mcconfigs/fifo.xml) is
presented below as an example.
``` xml
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/library/src/error/error.csv" />
<!-- Modes:
- NoStorage,
- Store (store data without errormodel),
- ErrorModel (store data with errormodel)
-->
<StoreMode value="NoStorage" />
<ControllerCoreDisableRefresh value="0"/>
</mcconfig>
<mcconfig>
<BankwiseLogic value="0"/>
<OpenPagePolicy value="1" />
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO" />
<Capsize value="5" />
<!-- 4 Modes: NoPowerDown, Staggered, TimeoutPDN, TimeoutSREF -->
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ControllerCoreDisableRefresh value="0"/>
<ControllerCoreForceMaxRefBurst value="0"/>
<ControllerCoreEnableRefPostpone value="0"/>
<ControllerCoreEnableRefPullIn value="0"/>
<ControllerCoreMaxPostponedARCmd value="8"/>
<ControllerCoreMaxPulledInARCmd value="8"/>
</mcconfig>
```
- *BankwiseLogic* (boolean)