derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,841 Commits 1 Branch 0 Tags
81bbe066c86928576030008f4170634e46beaf74
Commit Graph

1841 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Lukas Steiner
81bbe066c8 Markdown formatting. 2021-03-23 09:34:49 +01:00
Lukas Steiner
ba3c09b2ad Updated readme, code formatting. 2021-03-23 09:31:06 +01:00
Lukas Steiner
4650951026 Update gem5 readme. 2021-02-09 15:27:25 +01:00
Lukas Steiner
28b2fee54c Fix wrong standard display. 2021-02-09 15:08:27 +01:00
Lukas Steiner
2143f7cbff Set payload extensions in arbiter at END_REQ. 2021-02-02 16:40:44 +01:00
Lukas Steiner
0e01cc5ccd Fix starvation of new arbiters. 2021-02-02 15:34:21 +01:00
Lukas Steiner
fe144934b2 Use 1 as first payload ID. 2021-02-02 12:12:48 +01:00
Lukas Steiner
465bbdbe7e Add new configuration parameters for arbiter. 2021-02-02 12:08:31 +01:00
Lukas Steiner
28e7874a0e Fix bug in controller with ROB. 2021-02-02 12:07:52 +01:00
Lukas Steiner
a06bd9fc5b Minor changes in arbiter. 2021-01-27 13:57:01 +01:00
Lukas Steiner
d86dc97a28 Bugfix in fifo and reorder arbiter. 2021-01-27 13:12:36 +01:00
Lukas Steiner
a6ce8f63cb Improve command mux for multicycle commands, RAS/CAS bus missing. 2021-01-22 15:54:37 +01:00
Lukas Steiner
d198a78e5a Add new protocol to trace player. 2021-01-21 15:25:22 +01:00
Lukas Steiner
0f6611bacd Use sc_max_time() instead of SC_ZERO_TIME in all checkers. 2021-01-20 17:19:20 +01:00
Lukas Steiner
6c2b99a70a Fix fifo and reorder arbiter. 2021-01-20 15:29:55 +01:00
Lukas Steiner
0ab6562524 Add FW and BW think delay and PHY delay. 2021-01-20 14:20:44 +01:00
Lukas Steiner
3187c59183 Stagger refresh on different ranks. 2021-01-20 11:30:37 +01:00
Lukas Steiner
c50b089f76 Renaming of refresh policies. 2021-01-20 09:28:06 +01:00
Lukas Steiner
ca026981e1 Remove think delay from scheduler. 2021-01-20 08:50:15 +01:00
Lukas Steiner
020a01fd78 Only allow pointer to const for memspec. 2021-01-19 13:53:28 +01:00
Lukas Steiner
aff5802a7c Increase selectable area of a transaction in Trace Analyzer. 2021-01-19 13:49:02 +01:00
Lukas Steiner
679d70fa65 Increase selectable area of phases with zero span. 2021-01-15 11:13:11 +01:00
Lukas Steiner
abe8ef38b8 Implement first version of arbitration delay and think delay. 2021-01-14 16:48:21 +01:00
Lukas Steiner
a6684d95a4 Start adaption of fifo and reorder arbiter, not finished! 2021-01-14 14:27:53 +01:00
Lukas Steiner
87906da06b Adapt simple arbiter and STL player to new protocol. 2021-01-14 14:27:18 +01:00
Lukas Steiner
772e3a2e56 Upgrade controller to new protocol. 2021-01-14 11:29:45 +01:00
Lukas Steiner
e5e65a9323 Insert payload into scheduler after END_REQ. 2021-01-14 09:50:12 +01:00
Lukas Steiner
2845ebabc6 Increase time resolution in transaction tree widget. 2021-01-13 14:21:57 +01:00
Lukas Steiner
fbf117d0a9 Include PHY delay. 2021-01-13 11:33:21 +01:00
Lukas Steiner
c11db82a49 Merge branch 'gem5_fixes' into 'develop' 
Update gem5 coupling to latest gem5 version

See merge request ems/astdm/dram.sys!274
 2021-01-12 11:38:33 +01:00
Lukas Steiner
4e967b627f Fix sqlite3 missing header file bug. 2021-01-07 16:18:08 +01:00
Lukas Steiner
ac4566d157 Adapt gem5 paths. 2021-01-07 16:15:29 +01:00
Lukas Steiner
41108a269b Fix bandwidth calculation in TA. 2020-12-08 09:51:24 +01:00
Lukas Steiner
4aedeb8cc3 Merge branch 'power_and_buffer_analysis' into develop 
# Conflicts:
#	DRAMSys/traceAnalyzer/scripts/metrics.py
 2020-12-03 15:21:36 +01:00
Lukas Steiner
ccca87d633 Corrected idle phases calculation. 2020-12-03 14:28:18 +01:00
Matthias Jung
e9ccfaade7 Added RR and WW Miss 2020-12-02 10:00:15 +01:00
Matthias Jung
9355e03012 Changed Delay Reason to RW, WR and Other 2020-12-01 21:10:54 +01:00
Matthias Jung
a2ae5f8f49 Added bandwidth root cause analysis 2020-11-30 21:40:34 +01:00
Matthias Jung
ea01302a12 Improved the structure of the IDLE query 2020-11-30 19:17:04 +01:00
Lukas Steiner
d15ec81677 Add idle time at the simulation start to the total idle time. 2020-11-30 16:29:44 +01:00
Lukas Steiner
8c19ffa2fb Merge branch 'power_and_buffer_analysis' into database_fixes 2020-11-26 14:02:05 +01:00
Lukas Steiner
ce50dee0e2 Cleanup TLM recorder. 2020-11-26 13:57:07 +01:00
Matthias Jung
f008c0f4f6 Fixed a bug in memory idle calculation 
The python script was not correctly calculating the idle times for
traces with long pause times due to refreshes. Also out of order
scheduling would screw up this calculation.
 2020-11-25 22:03:02 +01:00
Lukas Steiner
efdba2c9ee Merge branch 'TA_dynamic_windows' into 'develop' 
TA Dynamic Windows and Fixes

See merge request ems/astdm/dram.sys!272
 2020-11-25 16:14:15 +01:00
Lukas Steiner
0f0eaf62bd Merge branch 'power_and_buffer_analysis' into TA_dynamic_windows 2020-11-25 15:28:59 +01:00
Lukas Steiner
e11420cecd Change initial splitter size in TA. 2020-11-25 15:27:47 +01:00
Lukas Steiner
2e652deaf4 Fix checkboxes in metrics window. 2020-11-25 15:02:08 +01:00
Matthias Jung
09eed96338 New delayed metric 2020-11-25 11:02:48 +01:00
Lukas Steiner
21afa61a6b Add splitters. 2020-11-23 17:32:07 +01:00
Lukas Steiner
2277a6b5f9 Merge branch 'power_and_buffer_analysis' into 'develop' 
Power and buffer analysis

See merge request ems/astdm/dram.sys!271
 2020-11-23 14:51:34 +01:00