Last fixes

Fix scrolling controller once and for all
External CAN working
2023-01-18 14:36:45 +01:00 · 2023-01-17 19:31:56 +01:00 · 2023-01-16 12:16:21 +01:00 · 2023-01-11 18:06:41 +01:00 · 2023-01-09 12:21:02 +01:00 · 2022-12-17 21:34:15 +01:00
13 changed files with 1013 additions and 158 deletions
--- a/programs/project.prog
+++ b/programs/project.prog
@@ -19,36 +19,41 @@ can_interrupt:
    nop

 .align
-led_addr: .word 0x000F0000
-switches_addr: .word 0x000F0004
 dmem_start_addr: .word 0x00000400
 dmem_end_addr: .word 0x000004FC
+
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+scrolling_addr: .word 0x000F00A0
+scrolling_count_addr: .word 0x000F00A4
+
 priority_mask: .word 0xFFFFFF03
+write_mask: .word 0x1000000
+clear_mask: .word 0x100
+scrolling_cnt_value: .word 0x10FC000 // for real board
+// scrolling_cnt_value: .word 0x500 // for simulation

 // CAN
 can_control_addr: .word 0x000F0100
 can_command_addr: .word 0x000F0101
+can_interrupt_addr: .word 0x000F0103
 can_acceptance_code_addr: .word 0x000F0104
 can_acceptance_mask_addr: .word 0x000F0105
 can_bus_timing0_addr: .word 0x000F0106
 can_bus_timing1_addr: .word 0x000F0107
 can_output_control_addr: .word 0x000F0108
-can_identifier0_addr: .word 0x000F010A
-can_identifier1_addr: .word 0x000F010B
-can_data0_addr: .word 0x000F010C
-can_data1_addr: .word 0x000F010D

 // CAN Constants
 acceptance_code: .word 0x00
 acceptance_mask: .word 0xFF
-// btr0: .word 0x45 Real board
-// btr1: .word 0x16 Real board
-btr0: .word 0x80
-btr1: .word 0x48
+btr0: .word 0x45 // for Real board
+btr1: .word 0x16 // for Real board
+// btr0: .word 0x80
+// btr1: .word 0x48
 output_control: .word 0x02
 control: .word 0xFE
-id0: .word 0xAA
-id1: .word 0xC2
+rx_interrupt_mask: .word 0x01
+tx_interrupt_mask: .word 0x02

 main:
    // Initialize stack pointer to the end of the data memory
@@ -83,60 +88,348 @@ main:
    ldr r3, >control
    st08 r0, r3

-    ldr r0, >can_identifier0_addr
-    ldr r3, >id0
-    st08 r0, r3
+    // Start scrolling controller
+    ldr r0, >scrolling_addr
+    clr r3
+    addi r3, 0x01
+    st32 r0, r3

-    ldr r0, >can_identifier1_addr
-    ldr r3, >id1
-    st08 r0, r3
+    // (Re)set scrolling speed
+    ldr r5, >scrolling_count_addr
+    ldr r4, >scrolling_cnt_value
+    st32 r5, r4

-    ldr r0, >can_data0_addr
+    // Set LED to state
+    ldr r0, >led_addr
    clr r3
    addi r3, 0x7A
    st08 r0, r3

-    ldr r0, >can_data1_addr
-    clr r3
-    addi r3, 0x4F
-    st08 r0, r3
-
-    // Wait some clks
-    call >wait
-
-    ldr r0, >can_command_addr
-    clr r3
-    addi r3, 0x01
-    st08 r0, r3
-
-    ldr r0, >led_addr
-    ldr r1, >switches_addr
-
-    st08 r0, r2
 loop:
    br >loop
    nop

-switches_interrupt_handler:
-    ld32 r2, r1
+.align
+button_data_add: .word 0x10000
+button_data_clear: .word 0x20000
+button_frequency: .word 0x40000

-    // Set LED to pattern
+switches_interrupt_handler:
+    // Read switch state
+    ldr r0, >switches_addr
+    ld32 r2, r0
+
+    ldr r0, >led_addr
    st08 r0, r2
+
+    clr r4
+
+    ldr r3, >button_data_clear
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_data_clear_frame
+    nop
+
+    ldr r3, >button_data_add
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_data_add_frame
+    nop
+
+    ldr r3, >button_frequency
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_frequency_frame
+    nop
+
+    // Unimplemented button function
    
    reti
    nop

 can_interrupt_handler:
+    // Dispatch interrupt event
+    ldr r0, >can_interrupt_addr
+    ld08 r1, r0
+    clr r4
+
+    ldr r2, >rx_interrupt_mask
+    and r5, r1, r2
+    cmp neq r5, r4
+    br true >can_rx_handler
+    nop
+
+    ldr r2, >tx_interrupt_mask
+    and r5, r1, r2
+    cmp neq r5, r4
+    br true >can_tx_handler
+    nop
+
+    // Unimplemented CAN interrupt
    reti
    nop

-wait:
-	clr r7
-    clr r8
-    addi r8, 16
-inc_i:
-	cmp neq r7,r8
-	br true >inc_i
-	addi r7,1
-	ret
+.align
+can_tx_data0_addr: .word 0x000F010C
+can_tx_data1_addr: .word 0x000F010D
+can_tx_data2_addr: .word 0x000F010E
+
+can_tx_identifier0_addr: .word 0x000F010A
+can_tx_identifier1_addr: .word 0x000F010B
+
+id0: .word 0xAA
+id1_0: .word 0xC1 // data length is also encoded here
+id1_1: .word 0xC2 // data length is also encoded here
+id1_2: .word 0xC3 // data length is also encoded here
+
+frame_data_add: .word 0x00
+frame_data_clear: .word 0x01
+frame_frequency: .word 0x02
+
+can_command_addr_ptr: .word =can_command_addr
+
+can_send_data_clear_frame:
+    ldr r0, >can_tx_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_tx_identifier1_addr
+    ldr r3, >id1_0
+    st08 r0, r3
+
+    ldr r0, >can_tx_data0_addr
+    ldr r3, >frame_data_clear
+    st08 r0, r3
+
+    // Save for tx interrupt
+    clr r6
+    add r6, r6, r3
+
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    reti
+    nop
+
+.align
+byte_mask: .word 0xFF
+
+can_send_data_add_frame:
+    ldr r0, >can_tx_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_tx_identifier1_addr
+    ldr r3, >id1_1
+    st08 r0, r3
+
+    ldr r0, >can_tx_data0_addr
+    ldr r3, >frame_data_add
+    st08 r0, r3
+
+    // Save for tx interrupt
+    clr r6
+    add r6, r6, r3
+
+    // r2 is still switches reg
+    ldr r0, >can_tx_data1_addr
+    st08 r0, r2
+
+    // Save for tx interrupt
+    clr r7
+    add r7, r7, r2
+    ldr r4, >byte_mask
+    and r7, r7, r4
+
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    reti
+    nop
+
+.align
+can_rx_data0_addr: .word 0x000F0116
+
+can_rx_handler:
+    // Dispatch CAN frame
+    ldr r0, >can_rx_data0_addr
+    ld08 r6, r0
+
+    ldr r2, >frame_data_clear
+    cmp eq r2, r6
+    br true >can_handle_data_clear_frame
+    nop
+
+    ldr r2, >frame_data_add
+    cmp eq r2, r6
+    br true >can_handle_data_add_frame
+    nop
+
+    ldr r2, >frame_frequency
+    cmp eq r2, r6
+    br true >can_handle_frequency_frame
+    nop
+
+    // Unimplemented CAN frame
+    reti
+    nop
+
+can_tx_handler:
+    // Dispatch CAN frame
+
+    ldr r2, >frame_data_clear
+    cmp eq r2, r6
+    br true >handle_data_clear_frame
+    nop
+
+    ldr r2, >frame_data_add
+    cmp eq r2, r6
+    br true >handle_data_add_frame
+    nop
+
+    ldr r2, >frame_frequency
+    cmp eq r2, r6
+    br true >handle_frequency_frame
+    nop
+
+    reti
+    nop
+
+can_send_frequency_frame:
+    ldr r0, >can_tx_identifier0_addr
+    ldr r3, >id0
+    st08 r0, r3
+
+    ldr r0, >can_tx_identifier1_addr
+    ldr r3, >id1_2
+    st08 r0, r3
+
+    ldr r0, >can_tx_data0_addr
+    ldr r3, >frame_frequency
+    st08 r0, r3
+
+    // Save for tx interrupt
+    clr r6
+    add r6, r6, r3
+
+    // r2 is still switches reg
+    ldr r0, >can_tx_data1_addr
+    st08 r0, r2
+
+    // Save for tx interrupt
+    clr r7
+    add r7, r7, r2
+    ldr r4, >byte_mask
+    and r7, r7, r4
+
+    ldr r0, >can_tx_data2_addr
+    rsh r2, r2, 8
+    st08 r0, r2
+
+    // Save for tx interrupt
+    clr r8
+    add r8, r8, r2
+    ldr r4, >byte_mask
+    and r8, r8, r4
+
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r3
+    addi r3, 0x01
+    st08 r0, r3
+
+    reti
+    nop
+
+can_handle_data_clear_frame:
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+handle_data_clear_frame:
+    ldr r0, >scrolling_addr_ptr
+    ldr r1, >clear_mask_ptr
+
+    ld32 r0, r0
+    ld32 r1, r1
+
+    st32 r0, r1
+
+    reti
+    nop
+
+.align
+scrolling_addr_ptr: .word =scrolling_addr
+write_mask_ptr: .word =write_mask
+can_command_addr_ptr0: .word =can_command_addr
+can_rx_data1_addr: .word 0x000F0117
+can_rx_data2_addr: .word 0x000F0118
+
+can_handle_data_add_frame:
+    ldr r0, >can_rx_data1_addr
+    ld08 r7, r0
+
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr0
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+handle_data_add_frame:
+    // Expect symbol to add in r7 register
+
+    ldr r0, >scrolling_addr_ptr
+    ld32 r0, r0
+
+    ldr r1, >write_mask_ptr
+    ld32 r1, r1
+
+    lsh r7, r7, 16
+    or r4, r7, r1
+    st32 r0, r4
+
+    reti
+    nop
+
+.align
+clear_mask_ptr: .word =clear_mask
+scrolling_count_addr_ptr: .word =scrolling_count_addr
+
+can_handle_frequency_frame:
+    ldr r0, >can_rx_data1_addr
+    ld08 r7, r0
+
+    ldr r0, >can_rx_data2_addr
+    ld08 r8, r0
+
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr0
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+handle_frequency_frame:
+    // Expect count value in r7 and r8 register
+
+    // For real board shift the count value by 16!
+
+    // Concat bits
+    lsh r8, r8, 8
+    or r8, r8, r7
+    lsh r8, r8, 16 // real board !!!
+
+    ldr r0, >scrolling_count_addr_ptr
+    ld32 r0, r0
+
+    st32 r0, r8
+
+    reti
    nop
--- a/programs/project_init.prog
+++ b/programs/project_init.prog
@@ -28,6 +28,7 @@ priority_mask: .word 0xFFFFFF03
 // CAN
 can_control_addr: .word 0x000F0100
 can_command_addr: .word 0x000F0101
+can_interrupt_addr: .word 0x000F0103
 can_acceptance_code_addr: .word 0x000F0104
 can_acceptance_mask_addr: .word 0x000F0105
 can_bus_timing0_addr: .word 0x000F0106
--- a/soc/peripheral/scrolling_buffer.vhd
+++ b/soc/peripheral/scrolling_buffer.vhd
@@ -65,25 +65,21 @@ begin
 		if clk'event and clk='1' then
 			if rst = '1' then
                ptr_read <= 0;
-                hex_char <= (others => '0');
+                hex_char <= (others => '1');
            else
-                hex_char <= (others => '0');
+                if ptr_last = -1 then -- Special case
+                    hex_char <= (others => '1');
+                else
+                    hex_char <= ring_buffer(ptr_read);
+                end if;
                
                if buffer_clear = '1' then
                    ptr_read <= 0;
-                else
-                    if next_char = '1' then
-                        if ptr_last = -1 then -- Special case
-                            hex_char <= (others => '0');
-                        else
-                            hex_char <= ring_buffer(ptr_read);
-    
-                            if ptr_read = ptr_last then
-                                ptr_read <= 0;
-                            else
-                                ptr_read <= ptr_read + 1;
-                            end if;
-                        end if;
+                elsif next_char = '1' then    
+                    if ptr_read = ptr_last then
+                        ptr_read <= 0;
+                    else
+                        ptr_read <= ptr_read + 1;
                    end if;
                end if;
            end if;
--- a/soc/peripheral/scrolling_controller.vhd
+++ b/soc/peripheral/scrolling_controller.vhd
@@ -25,10 +25,6 @@ architecture Behavioral of scrolling_controller is
    type state_type is (s_off, s_wait, s_update);
    signal state : state_type;
    
-    signal sig_seg_shift : std_logic;
-    signal sig_seg_write : std_logic;
-    signal sig_seg_clear : std_logic;
-    
    signal current_element : integer range 0 to 16;
    signal current_resetted : std_logic;

@@ -42,12 +38,11 @@ begin
                cnt_start <= '0';
                next_char <= '0';

-                sig_seg_shift <= '0';
-                sig_seg_write <= '0';
-                sig_seg_clear <= '0';
+                seg_shift <= '0';
+                seg_write <= '0';
+                seg_clear <= '0';

                current_element <= 0;
-                current_resetted <= '0';
            else
                case state is
                    when s_off =>
@@ -55,47 +50,52 @@ begin
                        
                        if on_off = '0' then
                            state <= s_off;
-                            sig_seg_shift <= '0';
-                            sig_seg_write <= '0';
-                            sig_seg_clear <= '0';
+                            seg_shift <= '0';
+                            seg_write <= '0';
+                            seg_clear <= '0';
                            cnt_start <= '0';
                            next_char <= '0';
                        else
-                            state <= s_wait;
-                            sig_seg_shift <= '0';
-                            sig_seg_write <= '0';
-                            sig_seg_clear <= '0';
+                            state <= s_update;
+                            -- seg_shift <= '1';
+                            -- seg_write <= '1';
+                            -- seg_off <= hex_char(4);
+                            -- seg_data <= hex_char(3 downto 0);
+                            -- seg_clear <= '0';
                            cnt_start <= '1';
                            next_char <= '0';
+                            current_element <= current_element + 1;
                        end if;
                    when s_wait =>
                        if on_off = '1' then
                            state <= s_off;
-                            sig_seg_clear <= '1';
+                            seg_clear <= '1';
+                            seg_write <= '0';
+                            seg_shift <= '0';
                            cnt_start <= '0';
                            next_char <= '0';
                        elsif cnt_done = '0' then
                            state <= s_wait;
-                            sig_seg_shift <= '0';
-                            sig_seg_write <= '0';
-                            sig_seg_clear <= '0';
+                            seg_shift <= '0';
+                            seg_write <= '0';
+                            seg_clear <= '0';
                            cnt_start <= '0';
                            next_char <= '0';
                        else -- cnt_done = '1'
                            state <= s_update;
-                            sig_seg_shift <= '0';
-                            sig_seg_write <= '0';
-                            sig_seg_clear <= '0';
+                            seg_shift <= '0';
+                            seg_write <= '0';
+                            seg_clear <= '0';
                            cnt_start <= '1';

-                            if current_element < unsigned(buffer_elements) then
-                                next_char <= '1';
-                            end if;
+                            -- if current_element < unsigned(buffer_elements) then
+                            --     next_char <= '1';
+                            -- else
+                                -- next_char <= '0';
+                            -- end if;

-                            current_resetted <= '0';
                            if current_element = 15 then
-                                current_element <= 0;
-                                current_resetted <= '1';
+                                current_element <= 1;
                            else
                                current_element <= current_element + 1;
                            end if;
@@ -103,14 +103,29 @@ begin
                    when s_update =>
                        if on_off = '0' then
                            state <= s_wait;
-                            sig_seg_shift <= '1';
-                            sig_seg_write <= '1';
-                            sig_seg_clear <= '0';
+                            seg_shift <= '1';
+                            seg_write <= '1';
+                            seg_clear <= '0';
                            cnt_start <= '0';
-                            next_char <= '0';
+                            
+                            if current_element <= unsigned(buffer_elements) then
+                                next_char <= '1';
+                            else
+                                next_char <= '0';
+                            end if;
+
+                            if current_element <= unsigned(buffer_elements) then
+                                seg_data <= hex_char(3 downto 0);
+                                seg_off <= hex_char(4);
+                            else
+                                seg_data <= x"0";
+                                seg_off <= '1';
+                            end if;
                        else
                            state <= s_off;
-                            sig_seg_clear <= '1';
+                            seg_clear <= '1';
+                            seg_write <= '0';
+                            seg_shift <= '0';
                            cnt_start <= '0';
                            next_char <= '0';
                        end if;
@@ -118,30 +133,5 @@ begin
            end if;
 		end if;
 	end process;
-	
-    process(clk)
-    begin
-        if clk'event and clk='1' then
-            if rst = '1' then
-                seg_data <= (others => '0');
-                seg_off <= '0';
-                seg_shift <= '0';
-                seg_write <= '0';
-                seg_clear <= '1';
-            else            
-                if current_element < unsigned(buffer_elements) and not (current_resetted = '1' and unsigned(buffer_elements) /= 16) then
-                    seg_data <= hex_char(3 downto 0);
-                    seg_off <= hex_char(4);
-                else
-                    seg_data <= x"0";
-                    seg_off <= '1';
-                end if;
-                
-                seg_clear <= sig_seg_clear;
-                seg_write <= sig_seg_write;
-                seg_shift <= sig_seg_shift;
-            end if;
-        end if;
-    end process;

 end Behavioral;
--- a/soc/peripheral/scrolling_timer.vhd
+++ b/soc/peripheral/scrolling_timer.vhd
@@ -17,7 +17,6 @@ architecture Behavioral of scrolling_timer is
 	signal counter : std_logic_vector(31 downto 0);
    signal done : std_logic;
    signal counting : std_logic;
-    signal value : std_logic_vector(31 downto 0);

 begin

@@ -29,10 +28,10 @@ begin
 				done <= '0';
 				counting <= '0';
 			else
-			    value <= cnt_value;
+                counter <= x"00000000";
                done <= '0';

-				if counter = value and counting = '1' then
+				if counter >= cnt_value and counting = '1' then
                    counter <= x"00000000";
                    done <= '1';
                    counting <= '0';
--- a/soc/peripheral/seven_segment_display.vhd
+++ b/soc/peripheral/seven_segment_display.vhd
@@ -54,8 +54,8 @@ begin
    );

    timer: simple_timer
-    -- generic map (timer_start => x"00000008") -- for simulation
-    generic map (timer_start => x"00000F00") -- for board
+    generic map (timer_start => x"00000008") -- for simulation
+    -- generic map (timer_start => x"00000F00") -- for board
    port map(
        clk => clk,
        rst => rst,
--- a/soc/peripheral/switches.vhd
+++ b/soc/peripheral/switches.vhd
@@ -64,7 +64,7 @@ begin
 		if clk'event and clk='1' then
 			if rst = '1' then
                interrupt <= '0';
-                old_input <= (others => '0');
+                old_input <= buttons & switches;
            else
                if buttons & switches /= old_input
                then
--- a/soc/testbench/project_2top.vhd
+++ b/soc/testbench/project_2top.vhd
@@ -20,20 +20,25 @@ ARCHITECTURE sim OF project_2top_tb IS

 	signal led0	: std_logic_vector(7 downto 0);
    signal led1	: std_logic_vector(7 downto 0);
-    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn0 : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn1 : std_logic_vector(4 downto 0) := (others => '0');
    signal sw : std_logic_vector(15 downto 0) := (others => '0');
    signal anodes0 : std_logic_vector(7 downto 0);
    signal cathodes0 : std_logic_vector(7 downto 0);
    signal anodes1 : std_logic_vector(7 downto 0);
    signal cathodes1 : std_logic_vector(7 downto 0);
+    signal rst_n : std_logic;
    
 	constant peer_num_inst : integer := 2;
 	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
 	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	
+	signal de : std_logic_vector(1 downto 0);
+	signal re_n : std_logic_vector(1 downto 0);

 	COMPONENT lt16soc_top IS
 		generic(
-			programfilename : string := "../../programs/project.ram"
+			programfilename : string := "../../programs/project_sim.ram"
 		);
 		port(
 			clk		: in  std_logic;
@@ -43,8 +48,10 @@ ARCHITECTURE sim OF project_2top_tb IS
 	        sw : in std_logic_vector(15 downto 0);
            anodes : out std_logic_vector(7 downto 0);
            cathodes : out std_logic_vector(7 downto 0);
-            can_rx_i : in std_logic;
-            can_tx_o : out std_logic
+            pmod_rxd : in std_logic;
+            pmod_txd : out std_logic;
+            pmod_de : out std_logic;
+            pmod_re_n : out std_logic
 		);
 	END COMPONENT;
 	
@@ -60,35 +67,33 @@ ARCHITECTURE sim OF project_2top_tb IS
 BEGIN

 	soc0: lt16soc_top
-    generic map(
-        programfilename => "../../programs/project.ram"
-    )
    port map(
 		clk=>clk,
 		rst=>rst,
 		led=>led0,
-		btn=>btn,
+		btn=>btn0,
 		sw=>sw,
        anodes=>anodes0,
        cathodes=>cathodes0,
-        can_rx_i=>rx_vector(0),
-        can_tx_o=>tx_vector(0)
+        pmod_rxd => rx_vector(0),
+        pmod_txd => tx_vector(0),
+        pmod_de => de(0),
+        pmod_re_n => re_n(0)
 	);

    soc1: lt16soc_top
-    generic map(
-        programfilename => "../../programs/project_init.ram"
-    )
    port map(
 		clk=>clk,
 		rst=>rst,
 		led=>led1,
-		btn=>btn,
+		btn=>btn1,
 		sw=>sw,
        anodes=>anodes1,
        cathodes=>cathodes1,
-        can_rx_i=>rx_vector(1),
-        can_tx_o=>tx_vector(1)
+        pmod_rxd => rx_vector(1),
+        pmod_txd => tx_vector(1),
+        pmod_de => de(1),
+        pmod_re_n => re_n(1)
 	);
        
    can_interconnect : phys_can_sim
@@ -96,7 +101,7 @@ BEGIN
        peer_num => peer_num_inst
    )
    port map(
-        rst => not rst,
+        rst => rst_n,
        rx_vector => rx_vector,
        tx_vector => tx_vector
    );
@@ -110,10 +115,44 @@ BEGIN
 	stimuli: process
 	begin
 		rst	<= '0';
+		sw <= x"000F";
+		
 		wait for CLK_PERIOD;
 		rst	<= '1';
-		wait for 300us;
+		
+		wait for 3us;
+		-- btn0 <= "00100"; -- freq
+		btn0 <= "00001"; -- add
+		-- btn0 <= "00010"; -- clear
+		
+		wait for 50us;
+		sw <= x"000A";
+		btn0 <= "00000";
+		btn1 <= "00001"; -- add		
+		
+		--wait for 50us;
+		--btn0 <= "00100"; -- freq
+		
+        wait for 50us;
+        sw <= x"1550";
+        btn0 <= "00000";
+		btn1 <= "00100"; -- freq
+		
+		wait for 500us;
+		btn0 <= "00010"; -- clear
+		
+        wait for 50us;
+		sw <= x"000C";
+		btn0 <= "00000";
+		btn1 <= "00001"; -- add	
+		
+        wait for 50us;
+		btn1 <= "00010"; -- clear
+				
+		wait for 100us;
 		assert false report "Simulation terminated!" severity failure;
 	end process stimuli;
+	
+	rst_n <= not rst;

 END ARCHITECTURE;
--- a/soc/top/external_can.vhd
+++ b/soc/top/external_can.vhd
@@ -0,0 +1,129 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/04/2023 01:55:04 PM
+-- Design Name: 
+-- Module Name: internal_can - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity external_can is
+port(
+	-- clock signal
+	clk		: in  std_logic;
+	-- external reset button
+	rst		: in std_logic;
+	
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    -- pmod
+    pmod_rxd : in std_logic_vector(1 downto 0);
+    pmod_txd : out std_logic_vector(1 downto 0);
+    pmod_de : out std_logic_vector(1 downto 0);
+    pmod_re_n : out std_logic_vector(1 downto 0)
+);
+end entity;
+
+architecture Behavioral of external_can is
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_rx_i : in std_logic;
+            can_tx_o : out std_logic
+		);
+	END COMPONENT;
+	
+    signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0');
+	signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0');
+	
+	signal anodes_cpy : std_logic_vector(7 downto 0);
+    signal cathodes_cpy : std_logic_vector(7 downto 0);
+    
+    signal led_cpy : std_logic_vector(7 downto 0);
+    
+    signal tx : std_logic_vector(1 downto 0);
+    
+    signal rst_n : std_logic;
+begin
+
+	soc0: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes_cpy,
+        cathodes=>cathodes_cpy,
+        can_rx_i=>pmod_rxd(0),
+        can_tx_o=>tx(0)
+	);
+
+    soc1: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led_cpy,
+		btn=>btn_cpy,
+		sw=>sw_cpy,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>pmod_rxd(1),
+        can_tx_o=>tx(1)
+	);
+    
+    -- TODO: für pmod !read enable auf low setzen
+    pmod_re_n <= (others => '0');
+    -- pmod_de <= (others => '1');
+    
+    pmod_de <= not tx;
+    pmod_txd <= tx;
+    
+    rst_n <= not rst;
+
+end Behavioral;
--- a/soc/top/internal_can.vhd
+++ b/soc/top/internal_can.vhd
@@ -0,0 +1,143 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 01/04/2023 01:55:04 PM
+-- Design Name: 
+-- Module Name: internal_can - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity internal_can is
+port(
+	-- clock signal
+	clk		: in  std_logic;
+	-- external reset button
+	rst		: in std_logic;
+	
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    can_rx_i : in std_logic;
+    can_tx_o : out std_logic
+);
+end entity;
+
+architecture Behavioral of internal_can is
+	COMPONENT lt16soc_top IS
+		generic(
+			programfilename : string := "../../programs/project.ram"
+		);
+		port(
+			clk		: in  std_logic;
+			rst		: in std_logic;
+			led		: out std_logic_vector(7 downto 0);
+			btn : in std_logic_vector(4 downto 0);
+	        sw : in std_logic_vector(15 downto 0);
+            anodes : out std_logic_vector(7 downto 0);
+            cathodes : out std_logic_vector(7 downto 0);
+            can_rx_i : in std_logic;
+            can_tx_o : out std_logic
+		);
+	END COMPONENT;
+	
+    component phys_can_sim 
+		generic(
+			peer_num : integer );
+		port(
+			rst : in std_logic;
+			rx_vector : out std_logic_vector(peer_num - 1 downto 0);
+			tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
+	end component phys_can_sim;
+	
+    constant peer_num_inst : integer := 2;
+	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	
+	signal rst_n : std_logic;
+	
+    signal btn_cpy : std_logic_vector(4 downto 0) := (others => '0');
+	signal sw_cpy : std_logic_vector(15 downto 0) := (others => '0');
+	
+	signal anodes_cpy : std_logic_vector(7 downto 0);
+    signal cathodes_cpy : std_logic_vector(7 downto 0);
+    
+    signal led_cpy : std_logic_vector(7 downto 0);
+begin
+
+	soc0: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led,
+		btn=>btn,
+		sw=>sw,
+        anodes=>anodes,
+        cathodes=>cathodes,
+        can_rx_i=>rx_vector(0),
+        can_tx_o=>tx_vector(0)
+	);
+
+    soc1: lt16soc_top
+    generic map(
+        programfilename => "../../programs/project.ram"
+    )
+    port map(
+		clk=>clk,
+		rst=>rst,
+		led=>led_cpy,
+		btn=>btn_cpy,
+		sw=>sw_cpy,
+        anodes=>anodes_cpy,
+        cathodes=>cathodes_cpy,
+        can_rx_i=>rx_vector(1),
+        can_tx_o=>tx_vector(1)
+	);
+	
+    can_interconnect : phys_can_sim
+    generic map(
+        peer_num => peer_num_inst
+    )
+    port map(
+        rst => rst_n,
+        rx_vector => rx_vector,
+        tx_vector => tx_vector
+    );
+    
+    rst_n <= not rst;
+    can_tx_o <= tx_vector(1);
+    
+    -- TODO: für pmod !read enable auf low setzen
+
+end Behavioral;
--- a/soc/top/top.vhd
+++ b/soc/top/top.vhd
@@ -14,7 +14,7 @@ use work.lt16soc_peripherals.all;

 entity lt16soc_top is
 generic(
-	programfilename : string := "../../programs/interrupt_test.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+	programfilename : string := "../../programs/project.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
 );
 port(
 	-- clock signal
@@ -30,8 +30,10 @@ port(
 	anodes : out std_logic_vector(7 downto 0);
    cathodes : out std_logic_vector(7 downto 0);

-    can_rx_i : in std_logic;
-    can_tx_o : out std_logic
+    pmod_rxd : in std_logic;
+    pmod_txd : out std_logic;
+    pmod_de : out std_logic;
+    pmod_re_n : out std_logic
 );
 end entity lt16soc_top;

@@ -60,6 +62,8 @@ architecture RTL of lt16soc_top is

 	signal irq_lines  : std_logic_vector((2 ** irq_num_width) - 1 downto 0) := (others=>'0');

+    signal can_tx : std_logic;
+
 	--//////////////////////////////////////////////////////
 	-- components
 	--//////////////////////////////////////////////////////
@@ -193,8 +197,8 @@ begin
        rstn	=> rst_gen,
        wbs_i	=> slvi(CFG_CAN),
        wbs_o	=> slvo(CFG_CAN),
-        rx_i	=> can_rx_i,
-        tx_o	=> can_tx_o,
+        rx_i	=> pmod_rxd,
+        tx_o	=> pmod_txd,
        irq_on	=> irq_lines(4)
    );

@@ -246,4 +250,8 @@ begin
            cathodes => cathodes
 		);

+    pmod_re_n <= '0';
+    pmod_de <= not can_tx;
+    pmod_txd <= can_tx;
+
 end architecture RTL;
--- a/soc/top/top.xdc
+++ b/soc/top/top.xdc
@@ -81,20 +81,20 @@ set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { btn[4]

 ##Pmod Headers
 ##Pmod Header JA
-set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { can_rx_i }]; #IO_L20N_T3_A19_15 Sch=ja[1]
-set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { can_tx_o }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
-#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
-#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
+set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { pmod_re_n }]; #IO_L20N_T3_A19_15 Sch=ja[1]
+set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { pmod_txd }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
+set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { pmod_rxd }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { pmod_de }]; #IO_L18N_T2_A23_15 Sch=ja[4]
 #set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
 #set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
 #set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
 #set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]

 ##Pmod Header JB
-#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
-#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
-#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
-#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
+#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { pmod_re_n[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
+#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { pmod_txd[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
+#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { pmod_rxd[1] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
+#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { pmod_de[1] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
 #set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
 #set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
 #set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
--- a/soc/top/top_project.vhd
+++ b/soc/top/top_project.vhd
@@ -0,0 +1,257 @@
+-- See the file "LICENSE" for the full license governing this code. --
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+library work;
+use work.lt16x32_internal.all;
+use work.lt16x32_global.all;
+use work.wishbone.all;
+use work.config.all;
+use work.lt16soc_memories.all;
+use work.lt16soc_peripherals.all;
+
+entity lt16soc_top_project is
+generic(
+	programfilename : string := "../../programs/project.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
+);
+port(
+	-- clock signal
+	clk		: in  std_logic;
+	-- external reset button
+	rst		: in std_logic;
+	
+	led		: out std_logic_vector(7 downto 0);
+	
+	btn : in std_logic_vector(4 downto 0);
+	sw : in std_logic_vector(15 downto 0);
+	
+	anodes : out std_logic_vector(7 downto 0);
+    cathodes : out std_logic_vector(7 downto 0);
+
+    pmod_rxd : in std_logic;
+    pmod_txd : out std_logic;
+    pmod_de : out std_logic;
+    pmod_re_n : out std_logic
+);
+end entity lt16soc_top_project;
+
+
+architecture RTL of lt16soc_top_project is
+	--//////////////////////////////////////////////////////
+	-- constant & signal
+	--//////////////////////////////////////////////////////
+
+	signal rst_gen	: std_logic;
+
+	constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1110_0000_0001";
+	constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
+
+	signal slvo	: wb_slv_out_vector := (others=> wbs_out_none);
+	signal msto	: wb_mst_out_vector := (others=> wbm_out_none);
+
+	signal slvi	: wb_slv_in_vector := (others=> wbs_in_none);
+	signal msti	: wb_mst_in_vector := (others=> wbm_in_none);
+
+	signal core2mem		: core_imem;
+	signal mem2core		: imem_core;
+
+	signal irq2core   : irq_core;
+	signal core2irq   : core_irq;
+
+	signal irq_lines  : std_logic_vector((2 ** irq_num_width) - 1 downto 0) := (others=>'0');
+
+    signal can_tx : std_logic;
+
+	--//////////////////////////////////////////////////////
+	-- components
+	--//////////////////////////////////////////////////////
+
+	component corewrapper
+	port(
+		clk       : in  std_logic;
+		rst       : in  std_logic;
+
+		in_imem   : in	imem_core;
+		out_imem  : out	core_imem;
+
+		in_proc   : in  irq_core;
+		out_proc  : out core_irq;
+
+		hardfault : out std_logic;
+
+		wmsti	:	in	wb_mst_in_type;
+		wmsto	:	out	wb_mst_out_type
+	);
+	end component;
+
+	component irq_controller
+	port(
+		clk       : in  std_logic;
+		rst       : in  std_logic;
+
+		in_proc   : in  core_irq;
+		out_proc  : out irq_core;
+
+		irq_lines : in  std_logic_vector((2 ** irq_num_width) - 1 downto 0)
+	);
+	end component;
+
+	component wb_intercon
+	generic(
+		slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"0000_0000_0000_0000";
+		mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"0000"
+	);
+	port(
+		clk		: in  std_logic;
+		rst		: in  std_logic;
+		msti	: out wb_mst_in_vector;
+		msto	: in  wb_mst_out_vector;
+		slvi	: out wb_slv_in_vector;
+		slvo	: in  wb_slv_out_vector
+	);
+	end component;
+
+begin
+
+	with RST_ACTIVE_HIGH select rst_gen	<=
+		rst when true,
+		not rst when others;
+
+	--//////////////////////////////////////////////////////
+	-- Instantiate
+	--//////////////////////////////////////////////////////
+
+	corewrap_inst: corewrapper
+	port map(
+		clk => clk,
+        rst => rst_gen,
+
+		in_imem		=> mem2core,
+		out_imem	=> core2mem,
+
+		in_proc		=> irq2core,
+		out_proc	=> core2irq,
+
+		hardfault	=> irq_lines(1),
+		wmsti		=> msti(CFG_LT16),
+		wmsto		=> msto(CFG_LT16)
+
+	);
+
+	irqcontr_inst: irq_controller
+	port map(
+		clk			=>	clk,
+		rst			=>	rst_gen,
+		in_proc		=>	core2irq,
+		out_proc	=>	irq2core,
+		irq_lines	=>	irq_lines
+	);
+
+	wbicn_inst: wb_intercon
+	generic map(
+		slv_mask_vector => slv_mask_vector,
+		mst_mask_vector => mst_mask_vector
+	)
+	port map(
+          clk => clk,
+          rst => rst_gen,
+          msti => msti,
+          msto => msto,
+          slvi => slvi,
+          slvo => slvo
+	);
+
+	memwrap_inst: memwrapper
+	generic map(
+		memaddr		=> CFG_BADR_MEM,
+		addrmask	=> CFG_MADR_MEM,
+		filename	=> programfilename,
+		size		=> IMEMSZ
+	)
+	port map(
+		clk 		=> clk,
+        rst 		=> rst_gen,
+		in_imem		=> core2mem,
+		out_imem	=> mem2core,
+
+		fault		=> irq_lines(2),
+		wslvi		=> slvi(CFG_MEM),
+		wslvo		=> slvo(CFG_MEM)
+	);
+
+	dmem : wb_dmem
+	generic map(
+		memaddr=>CFG_BADR_DMEM,
+		addrmask=>CFG_MADR_DMEM)
+	port map(clk,rst_gen,slvi(CFG_DMEM),slvo(CFG_DMEM));
+
+    can_inst : can_vhdl_top
+    generic map(
+        memaddr=>CFG_BADR_CAN,
+        addrmask=>CFG_MADR_CAN
+    )
+    port map(
+        clk	=> clk,
+        rstn	=> rst_gen,
+        wbs_i	=> slvi(CFG_CAN),
+        wbs_o	=> slvo(CFG_CAN),
+        rx_i	=> pmod_rxd,
+        tx_o	=> pmod_txd,
+        irq_on	=> irq_lines(4)
+    );
+
+	leddev : wb_led
+	generic map(
+		CFG_BADR_LED,
+        CFG_MADR_LED
+	)
+	port map(
+		clk,
+        rst_gen,
+        led,
+        slvi(CFG_LED),
+        slvo(CFG_LED)
+	);
+	
+    swdev : wb_switches
+	generic map(
+		CFG_BADR_SW,CFG_MADR_SW
+	)
+	port map(
+		clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw, irq_lines(3)
+	);
+	
+    timerdev : wb_timer
+	generic map(
+		CFG_BADR_TIMER,
+        CFG_MADR_TIMER
+	)
+	port map(
+		clk,
+        rst_gen,
+        slvi(CFG_TIMER),
+        slvo(CFG_TIMER)
+	);
+	
+    scrollingdev : wb_scrolling
+		generic map(
+			memaddr		=> CFG_BADR_SCR,
+			addrmask	=> CFG_MADR_SCR
+		)
+		port map(
+			clk		=> clk,
+			rst		=> rst_gen,
+			wslvi	=> slvi(CFG_SCR),
+			wslvo	=> slvo(CFG_SCR),
+
+            anodes => anodes,
+            cathodes => cathodes
+		);
+
+    pmod_re_n <= '0';
+    pmod_de <= not can_tx;
+    pmod_txd <= can_tx;
+
+end architecture RTL;
Author	SHA1	Message	Date
Derek Christ	911e27eede	Last fixes	2023-01-18 14:36:45 +01:00
Derek Christ	78d23f1459	Fix scrolling controller once and for all	2023-01-17 19:31:56 +01:00
Derek Christ	8636a9dcf5	External CAN working	2023-01-16 12:16:21 +01:00
Derek Christ	6aa0a3e8d9	Somewhat working	2023-01-11 18:06:41 +01:00
Derek Christ	480e79506e	Make program ready for real board	2023-01-09 12:21:02 +01:00
Derek Christ	df940404d9	Call RX handler on own TX interrupt	2022-12-17 21:34:15 +01:00
Derek Christ	d286704b8a	Code refactor	2022-12-17 21:10:14 +01:00
Derek Christ	3e173e9008	Update frequency over CAN working	2022-12-17 17:31:53 +01:00
Derek Christ	9794e697b3	Data add over CAN working	2022-12-17 17:02:06 +01:00
Derek Christ	9073e16e00	Clear over CAN working	2022-12-17 16:25:30 +01:00