derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
f3d4d6f2028684a85096d5023ba0f106438c1b5e
gem5/src/cpu
History
Gabe Black f3d4d6f202 cpu: Make the CPU's TLB parameter a BaseTLB. 
This is instead of the architecture specific version.

Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-11 09:34:40 +00:00
..
checker
cpu, power: Get rid of the remnants of the EA computation insts.
2018-01-09 03:02:26 +00:00
kvm
misc: Updates for gcc7.2 for x86
2017-12-14 00:27:59 +00:00
minor
cpu, power: Get rid of the remnants of the EA computation insts.
2018-01-09 03:02:26 +00:00
nocpu
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
o3
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
pred
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
simple
cpu, power: Get rid of the remnants of the EA computation insts.
2018-01-09 03:02:26 +00:00
testers
cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.
2017-12-20 09:25:32 +00:00
trace
cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper
2017-06-20 18:03:21 +00:00
activity.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
activity.hh
cpu: Useful getters for ActivityRecorder
2014-05-09 18:58:48 -04:00
base_dyn_inst_impl.hh
cpu, o3: consider split requests for LSQ checksnoop operations
2015-09-15 08:14:06 -05:00
base_dyn_inst.hh
cpu: Add a NotAnInst flag to the BaseDynInst class.
2018-01-09 03:03:04 +00:00
base.cc
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
base.hh
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
BaseCPU.py
cpu: Make the CPU's TLB parameter a BaseTLB.
2018-01-11 09:34:40 +00:00
CheckerCPU.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
cpuevent.cc
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
2006-06-06 17:32:21 -04:00
cpuevent.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
CPUTracers.py
cpu: Put all CPU instruction tracers in a single file
2015-01-25 07:22:17 -05:00
decode_cache.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
dummy_checker.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
dummy_checker.hh
cpu: Add header files for checker CPUs
2012-11-02 11:32:01 -05:00
DummyChecker.py
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
2013-02-15 17:40:08 -05:00
exec_context.cc
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
exec_context.hh
cpu, power: Get rid of the remnants of the EA computation insts.
2018-01-09 03:02:26 +00:00
exetrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
exetrace.hh
base: remove Trace::enabled flag
2015-09-30 15:21:55 -05:00
func_unit.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
func_unit.hh
cpu: Fix issue identified by UBSan
2015-07-30 03:41:22 -04:00
FuncUnit.py
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
2016-10-15 14:58:45 -05:00
inst_pb_trace.cc
base: remove Trace::enabled flag
2015-09-30 15:21:55 -05:00
inst_pb_trace.hh
misc: Remove redundant compiler-specific defines
2015-10-12 04:07:59 -04:00
inst_res.hh
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
inst_seq.hh
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
InstPBTrace.py
cpu: add support for outputing a protobuf formatted CPU trace
2015-02-16 03:32:38 -05:00
inteltrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
inteltrace.hh
base: remove Trace::enabled flag
2015-09-30 15:21:55 -05:00
intr_control_noisa.cc
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
intr_control.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
intr_control.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
IntrControl.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
nativetrace.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
nativetrace.hh
style: fix missing spaces in control statements
2016-02-06 17:21:19 -08:00
op_class.hh
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
2016-10-15 14:58:45 -05:00
pc_event.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
pc_event.hh
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
profile.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
profile.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
quiesce_event.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
quiesce_event.hh
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
reg_class_impl.hh
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
reg_class.cc
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
reg_class.hh
cpu: Added interface for vector reg file
2017-07-05 14:43:49 +00:00
SConscript
sim: add ExecMacro to Exec* compound debug flags
2015-10-06 17:26:50 -07:00
simple_thread.cc
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
simple_thread.hh
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
smt.hh
includes: fix up code after sorting
2011-04-15 10:44:14 -07:00
static_inst_fwd.hh
cpu: Don't forward declare RefCountingPtr
2014-08-13 06:57:26 -04:00
static_inst.cc
cpu: Add a pointer to a generic Nop StaticInst.
2017-12-22 00:27:20 +00:00
static_inst.hh
cpu: Add a pointer to a generic Nop StaticInst.
2017-12-22 00:27:20 +00:00
StaticInstFlags.py
arch: ISA parser additions of vector registers
2017-07-05 14:43:49 +00:00
thread_context.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
thread_context.hh
arch,cpu: "virtualize" the TLB interface.
2017-12-22 23:16:03 +00:00
thread_state.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
thread_state.hh
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
2017-02-27 14:10:15 -05:00
timebuf.hh
style: remove trailing whitespace
2016-02-06 17:21:18 -08:00
timing_expr.cc
cpu: Simplify the rename interface and use RegId
2017-07-05 14:43:49 +00:00
timing_expr.hh
arch: Use const StaticInstPtr references where possible
2014-09-27 09:08:36 -04:00
TimingExpr.py
cpu: `Minor' in-order CPU model
2014-07-23 16:09:04 -05:00
translation.hh
mem, cpu: Add a separate flag for strictly ordered memory
2015-05-05 03:22:33 -04:00