cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Idd5992463bcf9154f823b82461070d1f1842cea3
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3746
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

src/cpu/base.cc

@@ -229,8 +229,8 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
         if (p->function_trace_start == 0) {
             functionTracingEnabled = true;
         } else {
-            typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
-            Event *event = new wrap(this, true);
+            Event *event = new EventFunctionWrapper(
+                [this]{ enableFunctionTrace(); }, name(), true);
             schedule(event, p->function_trace_start);
         }
     }

src/cpu/kvm/base.cc

@@ -164,8 +164,7 @@ BaseKvmCPU::startup()
     thread->startup();
 
     Event *startupEvent(
-        new EventWrapper<BaseKvmCPU,
-                         &BaseKvmCPU::startupThread>(this, true));
+        new EventFunctionWrapper([this]{ startupThread(); }, name(), true));
     schedule(startupEvent, curTick());
 }
 

src/cpu/o3/probe/elastic_trace.cc

@@ -50,7 +50,7 @@
 
 ElasticTrace::ElasticTrace(const ElasticTraceParams* params)
     :  ProbeListenerObject(params),
-       regEtraceListenersEvent(this),
+       regEtraceListenersEvent([this]{ regEtraceListeners(); }, name()),
        firstWin(true),
        lastClearedSeqNum(0),
        depWindowSize(params->depWindowSize),

src/cpu/o3/probe/elastic_trace.hh

@@ -182,8 +182,7 @@ class ElasticTrace : public ProbeListenerObject
     void regStats();
 
     /** Event to trigger registering this listener for all probe points. */
-    EventWrapper<ElasticTrace,
-                 &ElasticTrace::regEtraceListeners> regEtraceListenersEvent;
+    EventFunctionWrapper regEtraceListenersEvent;
 
   private:
     /**

src/cpu/simple/timing.cc

@@ -80,7 +80,7 @@ TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
     : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
       dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
-      fetchEvent(this)
+      fetchEvent([this]{ fetch(); }, name())
 {
     _status = Idle;
 }

src/cpu/simple/timing.hh

@@ -159,7 +159,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
       public:
 
         TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
-            : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
+            : MasterPort(_name, _cpu), cpu(_cpu),
+              retryRespEvent([this]{ sendRetryResp(); }, name())
         { }
 
       protected:
@@ -176,7 +177,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
             void schedule(PacketPtr _pkt, Tick t);
         };
 
-        EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent;
+        EventFunctionWrapper retryRespEvent;
     };
 
     class IcachePort : public TimingCPUPort
@@ -315,8 +316,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
   private:
 
-    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
-    FetchEvent fetchEvent;
+    EventFunctionWrapper fetchEvent;
 
     struct IprEvent : Event {
         Packet *pkt;

src/cpu/testers/memtest/memtest.cc

@@ -86,9 +86,9 @@ MemTest::sendPkt(PacketPtr pkt) {
 
 MemTest::MemTest(const Params *p)
     : MemObject(p),
-      tickEvent(this),
-      noRequestEvent(this),
-      noResponseEvent(this),
+      tickEvent([this]{ tick(); }, name()),
+      noRequestEvent([this]{ noRequest(); }, name()),
+      noResponseEvent([this]{ noResponse(); }, name()),
       port("port", *this),
       retryPkt(nullptr),
       size(p->size),

src/cpu/testers/memtest/memtest.hh

@@ -84,15 +84,15 @@ class MemTest : public MemObject
 
     void tick();
 
-    EventWrapper<MemTest, &MemTest::tick> tickEvent;
+    EventFunctionWrapper tickEvent;
 
     void noRequest();
 
-    EventWrapper<MemTest, &MemTest::noRequest> noRequestEvent;
+    EventFunctionWrapper noRequestEvent;
 
     void noResponse();
 
-    EventWrapper<MemTest, &MemTest::noResponse> noResponseEvent;
+    EventFunctionWrapper noResponseEvent;
 
     class CpuPort : public MasterPort
     {

src/cpu/testers/traffic_gen/traffic_gen.cc

@@ -61,14 +61,14 @@ TrafficGen::TrafficGen(const TrafficGenParams* p)
       configFile(p->config_file),
       elasticReq(p->elastic_req),
       progressCheck(p->progress_check),
-      noProgressEvent(this),
+      noProgressEvent([this]{ noProgress(); }, name()),
       nextTransitionTick(0),
       nextPacketTick(0),
       currState(0),
       port(name() + ".port", *this),
       retryPkt(NULL),
       retryPktTick(0),
-      updateEvent(this),
+      updateEvent([this]{ update(); }, name()),
       numSuppressed(0)
 {
 }

src/cpu/testers/traffic_gen/traffic_gen.hh

@@ -152,7 +152,7 @@ class TrafficGen : public MemObject
     /**
      * Event to keep track of our progress, or lack thereof.
      */
-    EventWrapper<TrafficGen, &TrafficGen::noProgress> noProgressEvent;
+    EventFunctionWrapper noProgressEvent;
 
     /** Time of next transition */
     Tick nextTransitionTick;
@@ -206,7 +206,7 @@ class TrafficGen : public MemObject
     Tick retryPktTick;
 
     /** Event for scheduling updates */
-    EventWrapper<TrafficGen, &TrafficGen::update> updateEvent;
+    EventFunctionWrapper updateEvent;
 
     uint64_t numSuppressed;
 

src/cpu/trace/trace_cpu.cc

@@ -57,8 +57,8 @@ TraceCPU::TraceCPU(TraceCPUParams *params)
         icacheGen(*this, ".iside", icachePort, instMasterID, instTraceFile),
         dcacheGen(*this, ".dside", dcachePort, dataMasterID, dataTraceFile,
                   params),
-        icacheNextEvent(this),
-        dcacheNextEvent(this),
+        icacheNextEvent([this]{ schedIcacheNext(); }, name()),
+        dcacheNextEvent([this]{ schedDcacheNext(); }, name()),
         oneTraceComplete(false),
         traceOffset(0),
         execCompleteEvent(nullptr),

src/cpu/trace/trace_cpu.hh

@@ -1082,10 +1082,10 @@ class TraceCPU : public BaseCPU
     void schedDcacheNext();
 
     /** Event for the control flow method schedIcacheNext() */
-    EventWrapper<TraceCPU, &TraceCPU::schedIcacheNext> icacheNextEvent;
+    EventFunctionWrapper icacheNextEvent;
 
     /** Event for the control flow method schedDcacheNext() */
-    EventWrapper<TraceCPU, &TraceCPU::schedDcacheNext> dcacheNextEvent;
+    EventFunctionWrapper dcacheNextEvent;
 
     /** This is called when either generator finishes executing from the trace */
     void checkAndSchedExitEvent();

src/gpu-compute/gpu_tlb.cc

@@ -61,7 +61,9 @@ namespace X86ISA
 
     GpuTLB::GpuTLB(const Params *p)
         : MemObject(p), configAddress(0), size(p->size),
-          cleanupEvent(this, false, Event::Maximum_Pri), exitEvent(this)
+          cleanupEvent([this]{ cleanup(); }, name(), false,
+                       Event::Maximum_Pri),
+          exitEvent([this]{ exitCallback(); }, name())
     {
         assoc = p->assoc;
         assert(assoc <= size);

src/gpu-compute/gpu_tlb.hh

@@ -425,7 +425,7 @@ namespace X86ISA
         // free memory and do the required clean-up
         void cleanup();
 
-        EventWrapper<GpuTLB, &GpuTLB::cleanup> cleanupEvent;
+        EventFunctionWrapper cleanupEvent;
 
         /**
          * This hash map will use the virtual page address as a key
@@ -458,7 +458,7 @@ namespace X86ISA
         // Called at the end of simulation to dump page access stats.
         void exitCallback();
 
-        EventWrapper<GpuTLB, &GpuTLB::exitCallback> exitEvent;
+        EventFunctionWrapper exitEvent;
     };
 }