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misc: Updates for gcc7.2 for x86

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GCC 7.2 is much stricter than previous GCC versions. The following changes
are needed:

* There is now a warning if there is an implicit fallthrough between two
  case statments. C++17 adds the [[fallthrough]]; declaration. However,
  to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH.
  M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and
  if that doesn't exist, it defaults to nothing (no older compilers
  generate warnings).
* The above resulted in a couple of bugs that were found. This is noted
  in the review request on gerrit.
* throw() for dynamic exception specification is deprecated
* There were a couple of new uninitialized variable warnings
* Can no longer perform bitwise operations on a bool.
* Must now include <functional> for std::function
* Compiler bug for void* lambda. Changed to auto as work around. See
  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878

Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/5802
Reviewed-by: Gabe Black <gabeblack@google.com>
This commit is contained in:
Jason Lowe-Power
2017-12-13 10:19:04 -08:00
parent f07d5069d8
commit 5c41076bd7
21 changed files with 54 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
ext/dnet/ip.h
View File

@@ -428,47 +428,13 @@ inline int
ip_cksum_add(const void *buf, size_t len, int cksum)
{
uint16_t *sp = (uint16_t *)buf;
int n, sn;
int sn;
sn = len / 2;
n = (sn + 15) / 16;
/* XXX - unroll loop using Duff's device. */
switch (sn % 16) {
case 0: do {
cksum += *sp++;
case 15:
cksum += *sp++;
case 14:
cksum += *sp++;
case 13:
cksum += *sp++;
case 12:
cksum += *sp++;
case 11:
cksum += *sp++;
case 10:
cksum += *sp++;
case 9:
cksum += *sp++;
case 8:
cksum += *sp++;
case 7:
cksum += *sp++;
case 6:
cksum += *sp++;
case 5:
cksum += *sp++;
case 4:
cksum += *sp++;
case 3:
cksum += *sp++;
case 2:
cksum += *sp++;
case 1:
cksum += *sp++;
} while (--n > 0);
}
do {
cksum += *sp++;
} while (--sn > 0);
if (len & 1)
cksum += htons(*(u_char *)sp << 8);

1
ext/drampower/src/Utils.h
View File

@@ -46,7 +46,6 @@
template<typename T>
T fromString(const std::string& s,
std::ios_base& (*f)(std::ios_base &) = std::dec)
throw(std::runtime_error)
{
std::istringstream is(s);
T t;

3
src/arch/arm/isa.cc
View File

@@ -1653,6 +1653,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
}
}
M5_FALLTHROUGH;
case MISCREG_TTBR0:
case MISCREG_TTBR1:
{
@@ -1666,12 +1667,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
}
}
}
M5_FALLTHROUGH;
case MISCREG_SCTLR_EL1:
{
tc->getITBPtr()->invalidateMiscReg();
tc->getDTBPtr()->invalidateMiscReg();
setMiscRegNoEffect(misc_reg, newVal);
}
M5_FALLTHROUGH;
case MISCREG_CONTEXTIDR:
case MISCREG_PRRR:
case MISCREG_NMRR:

1
src/arch/arm/table_walker.cc
View File

@@ -1398,6 +1398,7 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
warn_if(!attr_hi, "Unpredictable behavior");
M5_FALLTHROUGH;
case 0x4: // Device-nGnRE memory or
// Normal memory, Inner Non-cacheable
case 0x8: // Device-nGRE memory or

4
src/arch/x86/isa.cc
View File

@@ -316,7 +316,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
break;
case MISCREG_DR4:
miscReg = MISCREG_DR6;
/* Fall through to have the same effects as DR6. */
M5_FALLTHROUGH;
case MISCREG_DR6:
{
DR6 dr6 = regVal[MISCREG_DR6];
@@ -333,7 +333,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
break;
case MISCREG_DR5:
miscReg = MISCREG_DR7;
/* Fall through to have the same effects as DR7. */
M5_FALLTHROUGH;
case MISCREG_DR7:
{
DR7 dr7 = regVal[MISCREG_DR7];

3
src/arch/x86/isa/microops/regop.isa
View File

@@ -1427,6 +1427,7 @@ let {{
if (bits(newVal, 63, 4))
fault = std::make_shared<GeneralProtection>(0);
}
break;
default:
fault = std::make_shared<GenericISA::M5PanicFault>(
"Unrecognized control register %d.\\n", dest);
@@ -1528,7 +1529,7 @@ let {{
fault = std::make_shared<GeneralProtection>(selector);
break;
}
// Fall through on purpose
M5_FALLTHROUGH;
case SegIntGateCheck:
// Make sure the gate's the right type.
if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||

14
src/base/compiler.hh
View File

@@ -63,6 +63,20 @@
# define M5_CLASS_VAR_USED
#endif
// This can be removed once all compilers support C++17
#if defined __has_cpp_attribute
// Note: We must separate this if statement because GCC < 5.0 doesn't
// support the function-like syntax in #if statements.
#if __has_cpp_attribute(fallthrough)
#define M5_FALLTHROUGH [[fallthrough]]
#else
#define M5_FALLTHROUGH
#endif
#else
// Unsupported (and no warning) on GCC < 7.
#define M5_FALLTHROUGH
#endif
// std::make_unique redefined for C++11 compilers
namespace m5
{

6
src/base/cprintf.cc
View File

@@ -35,6 +35,8 @@
#include <iostream>
#include <sstream>
#include "base/compiler.hh"
using namespace std;
namespace cp {
@@ -138,6 +140,7 @@ Print::process_flag()
case 'X':
fmt.uppercase = true;
M5_FALLTHROUGH;
case 'x':
fmt.base = Format::hex;
fmt.format = Format::integer;
@@ -159,6 +162,7 @@ Print::process_flag()
case 'G':
fmt.uppercase = true;
M5_FALLTHROUGH;
case 'g':
fmt.format = Format::floating;
fmt.float_format = Format::best;
@@ -167,6 +171,7 @@ Print::process_flag()
case 'E':
fmt.uppercase = true;
M5_FALLTHROUGH;
case 'e':
fmt.format = Format::floating;
fmt.float_format = Format::scientific;
@@ -213,6 +218,7 @@ Print::process_flag()
fmt.fill_zero = true;
break;
}
M5_FALLTHROUGH;
case '1':
case '2':
case '3':

2
src/base/imgwriter.cc
View File

@@ -59,7 +59,7 @@ createImgWriter(Enums::ImageFormat type, const FrameBuffer *fb)
// gem5 will try PNG first, and it will fallback to BMP if not
// available.
/* FALLTHROUGH */
M5_FALLTHROUGH;
#if USE_PNG
case Enums::Png:
return std::unique_ptr<PngWriter>(new PngWriter(fb));

2
src/cpu/kvm/base.cc
View File

@@ -383,7 +383,7 @@ BaseKvmCPU::drain()
deschedule(tickEvent);
_status = Idle;
/** FALLTHROUGH */
M5_FALLTHROUGH;
case Idle:
// Idle, no need to drain
assert(!tickEvent.scheduled());

6
src/cpu/kvm/x86_cpu.cc
View File

@@ -396,6 +396,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_ES:
if (seg.unusable)
break;
M5_FALLTHROUGH;
case MISCREG_CS:
if (seg.base & 0xffffffff00000000ULL)
warn("Illegal %s base: 0x%x\n", name, seg.base);
@@ -433,7 +434,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case 3:
if (sregs.cs.type == 3 && seg.dpl != 0)
warn("CS type is 3, but SS DPL is != 0.\n");
/* FALLTHROUGH */
M5_FALLTHROUGH;
case 7:
if (!(sregs.cr0 & 1) && seg.dpl != 0)
warn("SS DPL is %i, but CR0 PE is 0\n", seg.dpl);
@@ -477,6 +478,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_GS:
if (seg.unusable)
break;
M5_FALLTHROUGH;
case MISCREG_CS:
if (!seg.s)
warn("%s: S flag not set\n", name);
@@ -485,6 +487,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_TSL:
if (seg.unusable)
break;
M5_FALLTHROUGH;
case MISCREG_TR:
if (seg.s)
warn("%s: S flag is set\n", name);
@@ -500,6 +503,7 @@ checkSeg(const char *name, const int idx, const struct kvm_segment &seg,
case MISCREG_TSL:
if (seg.unusable)
break;
M5_FALLTHROUGH;
case MISCREG_TR:
case MISCREG_CS:
if (!seg.present)

1
src/cpu/minor/dyn_inst.cc
View File

@@ -169,6 +169,7 @@ printRegName(std::ostream &os, const RegId& reg)
break;
case CCRegClass:
os << 'c' << static_cast<unsigned int>(reg.index());
break;
default:
panic("Unknown register class: %d", (int)reg.classValue());
}

4
src/dev/arm/generic_timer.cc
View File

@@ -385,7 +385,7 @@ GenericTimer::setMiscReg(int reg, unsigned cpu, MiscReg val)
case MISCREG_CNTPS_CVAL_EL1:
case MISCREG_CNTPS_TVAL_EL1:
case MISCREG_CNTPS_CTL_EL1:
/* FALLTHROUGH */
M5_FALLTHROUGH;
// PL2 phys. timer, non-secure
case MISCREG_CNTHCTL:
@@ -466,7 +466,7 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
case MISCREG_CNTPS_CVAL_EL1:
case MISCREG_CNTPS_TVAL_EL1:
case MISCREG_CNTPS_CTL_EL1:
/* FALLTHROUGH */
M5_FALLTHROUGH;
// PL2 phys. timer, non-secure
case MISCREG_CNTHCTL:

9
src/dev/net/i8254xGBe.cc
View File

@@ -2290,14 +2290,13 @@ IGbE::rxStateMachine()
int descLeft = rxDescCache.descLeft();
DPRINTF(EthernetSM, "RXS: descLeft: %d rdmts: %d rdlen: %d\n",
descLeft, regs.rctl.rdmts(), regs.rdlen());
switch (regs.rctl.rdmts()) {
case 2: if (descLeft > .125 * regs.rdlen()) break;
case 1: if (descLeft > .250 * regs.rdlen()) break;
case 0: if (descLeft > .500 * regs.rdlen()) break;
// rdmts 2->1/8, 1->1/4, 0->1/2
int ratio = (1ULL << (regs.rctl.rdmts() + 1));
if (descLeft * ratio <= regs.rdlen()) {
DPRINTF(Ethernet, "RXS: Interrupting (RXDMT) "
"because of descriptors left\n");
postInterrupt(IT_RXDMT);
break;
}
if (rxFifo.empty())

2
src/dev/pci/copy_engine.cc
View File

@@ -249,7 +249,7 @@ CopyEngine::CopyEngineChannel::channelRead(Packet *pkt, Addr daddr, int size)
break;
case CHAN_STATUS:
assert(size == sizeof(uint64_t));
pkt->set<uint64_t>(cr.status() | ~busy);
pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
break;
case CHAN_CHAINADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));

1
src/dev/storage/ide_disk.cc
View File

@@ -705,6 +705,7 @@ IdeDisk::startCommand()
// Supported DMA commands
case WDCC_WRITEDMA:
dmaRead = true; // a write to the disk is a DMA read from memory
M5_FALLTHROUGH;
case WDCC_READDMA:
if (!(cmdReg.drive & DRIVE_LBA_BIT))
panic("Attempt to perform CHS access, only supports LBA\n");

2
src/dev/x86/i8042.cc
View File

@@ -455,10 +455,12 @@ X86ISA::I8042::write(PacketPtr pkt)
case WriteOutputPort:
warn("i8042 \"Write output port\" command not implemented.\n");
lastCommand = WriteOutputPort;
break;
case WriteKeyboardOutputBuff:
warn("i8042 \"Write keyboard output buffer\" "
"command not implemented.\n");
lastCommand = WriteKeyboardOutputBuff;
break;
case WriteMouseOutputBuff:
DPRINTF(I8042, "Got command to write to mouse output buffer.\n");
lastCommand = WriteMouseOutputBuff;

2
src/kern/linux/printk.cc
View File

@@ -101,6 +101,7 @@ Printk(stringstream &out, Arguments args)
break;
case 'P':
format = true;
M5_FALLTHROUGH;
case 'p':
hexnum = true;
break;
@@ -258,4 +259,3 @@ Printk(stringstream &out, Arguments args)
}
}

1
src/mem/slicc/symbols/Type.py
View File

@@ -734,6 +734,7 @@ ${{self.c_ident}}_base_number(const ${{self.c_ident}}& obj)
code(' base += ${{enum.ident}}_Controller::getNumControllers();')
else:
code(' base += 0;')
code(' M5_FALLTHROUGH;')
code(' case ${{self.c_ident}}_${{enum.ident}}:')
code(' break;')
code.dedent()

1
src/sim/eventq.hh
View File

@@ -41,6 +41,7 @@
#include <algorithm>
#include <cassert>
#include <climits>
#include <functional>
#include <iosfwd>
#include <memory>
#include <mutex>

3
src/sim/fd_array.cc
View File

@@ -131,8 +131,7 @@ FDArray::restoreFileOffsets()
* possible to guarantee that the simulation will proceed as it should
* have in the same way that it would have proceeded sans checkpoints.
*/
void (*seek)(std::shared_ptr<FileFDEntry>)
= [] (std::shared_ptr<FileFDEntry> ffd)
auto seek = [] (std::shared_ptr<FileFDEntry> ffd)
{
if (lseek(ffd->getSimFD(), ffd->getFileOffset(), SEEK_SET) < 0)
fatal("Unable to seek to location in %s", ffd->getFileName());