Gabe Black eec8ac1595 fastmodel: Implement readVecRegFlat for ArmThreadContext. ...

This just calls readVecReg after constructing a RegId.

Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

2019-12-24 04:22:28 +00:00

..

alpha

sim,arch: Collapse the ISA specific versions of m5Syscall.

2019-12-10 23:58:14 +00:00

arm

fastmodel: Implement readVecRegFlat for ArmThreadContext.

2019-12-24 04:22:28 +00:00

generic

sim,arch: Collapse the ISA specific versions of m5Syscall.

2019-12-10 23:58:14 +00:00

hsail

arch-hsail: changed gen.py shebang from python(3) to python2.7

2019-03-11 22:13:24 +00:00

mips

sim,arch: Collapse the ISA specific versions of m5Syscall.

2019-12-10 23:58:14 +00:00

null

cpu, arch: Replace the CCReg type with RegVal.

2019-02-01 01:22:19 +00:00

power

sim,arch: Collapse the ISA specific versions of m5Syscall.

2019-12-10 23:58:14 +00:00

riscv

sim,arch: Collapse the ISA specific versions of m5Syscall.

2019-12-10 23:58:14 +00:00

sparc

sim,arch: Collapse the ISA specific versions of m5Syscall.

2019-12-10 23:58:14 +00:00

x86

x86: Fix some bugs with KVM in SE mode on Intel machines.

2019-12-18 04:38:20 +00:00

isa_parser.py

arch: Add include guards to auto-gen. decode header

2019-05-30 15:56:17 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "interrupts.hh" switching header file.

2019-10-19 01:46:00 +00:00