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fastmodel: Implement readVecRegFlat for ArmThreadContext.

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This just calls readVecReg after constructing a RegId.

Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2019-11-05 15:45:07 -08:00
parent 231dc99c84
commit eec8ac1595
2 changed files with 7 additions and 0 deletions
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6
src/arch/arm/fastmodel/iris/arm/thread_context.cc
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@@ -201,6 +201,12 @@ ArmThreadContext::readVecReg(const RegId &reg_id) const
return reg;
}
const ArmISA::VecRegContainer &
ArmThreadContext::readVecRegFlat(RegIndex idx) const
{
return readVecReg(RegId(VecRegClass, idx));
}
Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({
{ ArmISA::MISCREG_CPSR, "CPSR" },
{ ArmISA::MISCREG_SPSR, "SPSR" },

1
src/arch/arm/fastmodel/iris/arm/thread_context.hh
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@@ -83,6 +83,7 @@ class ArmThreadContext : public Iris::ThreadContext
}
const VecRegContainer &readVecReg(const RegId &reg) const override;
const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
};
} // namespace Iris