diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
index 8a36ce3d34..c48ade817c 100644
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
@@ -201,6 +201,12 @@ ArmThreadContext::readVecReg(const RegId &reg_id) const
     return reg;
 }
 
+const ArmISA::VecRegContainer &
+ArmThreadContext::readVecRegFlat(RegIndex idx) const
+{
+    return readVecReg(RegId(VecRegClass, idx));
+}
+
 Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({
         { ArmISA::MISCREG_CPSR, "CPSR" },
         { ArmISA::MISCREG_SPSR, "SPSR" },
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
index c7f26e3bd0..8344f57b83 100644
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
@@ -83,6 +83,7 @@ class ArmThreadContext : public Iris::ThreadContext
     }
 
     const VecRegContainer &readVecReg(const RegId &reg) const override;
+    const VecRegContainer &readVecRegFlat(RegIndex idx) const override;
 };
 
 } // namespace Iris