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x86: Fix some bugs with KVM in SE mode on Intel machines.

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The granularity bit should be set since the segment limit should be
interpreted as a number of pages, not bytes.

A comment indicates that NX support is enabled, but the bit wasn't
being set. That's now set to be consistent with FS mode.

The SVME bit is now turned off, since Intel CPUs don't have SVME, and
enabling it apparently makes them upset.

Also disable CR4 bits which enable features neither gem5 nor apparently
my workstation support.

Change-Id: I72d5a07871dede8763b0dd188a52fe5eb6bde6ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23361
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-12-03 20:35:22 -08:00
parent d040db5361
commit 3723cda9c2
1 changed files with 5 additions and 4 deletions
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9
src/arch/x86/process.cc
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@@ -235,6 +235,7 @@ X86_64Process::initState()
initDesc.p = 1; // present
initDesc.l = 1; // longmode - 64 bit
initDesc.d = 0; // operand size
initDesc.g = 1;
initDesc.s = 1; // system segment
initDesc.limit = 0xFFFFFFFF;
initDesc.base = 0;
@@ -376,8 +377,8 @@ X86_64Process::initState()
efer.sce = 1; // Enable system call extensions.
efer.lme = 1; // Enable long mode.
efer.lma = 1; // Activate long mode.
efer.nxe = 0; // Enable nx support.
efer.svme = 1; // Enable svm support for now.
efer.nxe = 1; // Enable nx support.
efer.svme = 0; // Enable svm support for now.
efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
tc->setMiscReg(MISCREG_EFER, efer);
@@ -406,8 +407,8 @@ X86_64Process::initState()
CR4 cr4 = 0;
//Turn on pae.
cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
cr4.osxsave = 0; // Enable XSAVE and Proc Extended States
cr4.osxmmexcpt = 0; // Operating System Unmasked Exception
cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
cr4.pce = 0; // Performance-Monitoring Counter Enable
cr4.pge = 0; // Page-Global Enable