Giacomo Travaglini e412ddddbd arch-arm: Split takeInt into AArch64/32 versions ...

We pay a small duplication cost but we make the code
more readable and we enable further modifications to the
AArch64 code without forcing the same code on the AArch32
method

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I1efa33cf19f91094fd33bd48b6a0a57d8df8f89f

2023-10-10 09:45:59 +01:00

..

amdgpu

gpu-compute,arch-vega: Implement flat scratch insts

2023-08-26 13:40:12 -05:00

arm

arch-arm: Split takeInt into AArch64/32 versions

2023-10-10 09:45:59 +01:00

generic

arch: Adding missing override to PCState.set

2023-10-05 10:18:19 -07:00

isa_parser

arch: Enable customized decoder class name

2023-09-22 15:45:56 +08:00

mips

arch,base,dev,sim: Convert objects to use the HostSocket param type.

2023-04-12 02:18:22 +00:00

null

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00

power

arch-power: Fix reporting traps to GDB

2023-08-17 15:55:04 +01:00

riscv

arch-riscv: Implement Zcb instructions

2023-10-05 18:46:35 +08:00

sparc

misc: Fix 'unused variable' clang errors with gem5.fast

2023-05-08 22:54:06 +00:00

x86

tests,misc: Fix compilation tests failures (#400)

2023-10-09 11:20:52 -07:00

micro_asm_test.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

micro_asm.py

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

SConscript

arch,cpu: Add boilerplate support for matrix registers

2023-01-17 10:09:56 +00:00

SConsopts

misc: Replace TARGET_ISA with USE_${ISA} variables.

2022-09-02 10:20:51 +00:00