derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
da740b1cdd9e213fb740f3401a5d61bf7be10b10
gem5/src/mem/ruby/protocol
History
Giacomo Travaglini da740b1cdd mem-ruby: Add a DBID field to the CHIResponseMsg data type 
This will hold the CHI Data Buffer Identifier (DBID) field.
The DBID allows a Completer of a transaction to provide its own
identifier for a transaction ID.
This new ID will be used as a TxnId field by a following
WriteData/CompData/CompAck response.

For now we only set it to the original txnId (identity mapping)

Change-Id: If30c5e1cafbe5a30073c7cd01d60bf41eb586cee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-09-08 08:38:13 +01:00
..
chi
mem-ruby: Add a DBID field to the CHIResponseMsg data type
2023-09-08 08:38:13 +01:00
Garnet_standalone-cache.sm
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
Garnet_standalone-dir.sm
mem: Delete authors lists from mem files.
2020-02-17 21:51:08 +00:00
Garnet_standalone-msg.sm
…
Garnet_standalone.slicc
…
GPU_VIPER-msg.sm
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
GPU_VIPER-SQC.sm
mem-ruby, gpu-compute: update TCP,SQC to pass hit/miss
2022-06-21 22:59:05 +00:00
GPU_VIPER-TCC.sm
mem: Atomic ops to same address
2023-08-23 14:45:25 -05:00
GPU_VIPER-TCP.sm
mem-ruby: add GPU cache bypass I->I transition
2023-01-08 20:24:11 +00:00
GPU_VIPER.slicc
mem-ruby: Add DMA support to MOESI_AMD_Base-dir.sm
2020-06-19 20:34:06 +00:00
MESI_Three_Level_HTM-L0cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MESI_Three_Level_HTM.slicc
mem-ruby: HTM mem implementation
2020-09-08 09:13:30 +00:00
MESI_Three_Level-L0cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MESI_Three_Level-L1cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MESI_Three_Level-msg.sm
mem-ruby: HTM mem implementation
2020-09-08 09:13:30 +00:00
MESI_Three_Level.slicc
…
MESI_Two_Level-dir.sm
mem-ruby: Fix of an address bug in MESI_Two_Level-dir.sm
2023-07-07 10:17:54 +00:00
MESI_Two_Level-dma.sm
…
MESI_Two_Level-L1cache.sm
mem-ruby: Fix replacement policy in MESI_Two_Level
2022-10-20 01:03:39 +00:00
MESI_Two_Level-L2cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MESI_Two_Level-msg.sm
…
MESI_Two_Level.slicc
…
MI_example-cache.sm
mem-ruby: Fix replacement policy updates with stores in MI_example
2022-09-09 15:19:54 +00:00
MI_example-dir.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
MI_example-dma.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MI_example-msg.sm
…
MI_example.slicc
…
MOESI_AMD_Base-CorePair.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_AMD_Base-dir.sm
mem-ruby: Reorder SLC atomic and response actions
2023-09-01 10:36:54 -05:00
MOESI_AMD_Base-dma.sm
mem-ruby: Add protocol prints to MOESI_AMD_BASE-dma
2022-02-17 17:03:19 +00:00
MOESI_AMD_Base-L3cache.sm
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
MOESI_AMD_Base-msg.sm
gpu-compute, mem-ruby: Update GPU cache bypassing to use TBE
2023-01-05 23:38:32 +00:00
MOESI_AMD_Base-probeFilter.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
MOESI_AMD_Base-Region-CorePair.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_AMD_Base-Region-dir.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
MOESI_AMD_Base-Region-msg.sm
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
MOESI_AMD_Base-RegionBuffer.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_AMD_Base-RegionDir.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_AMD_Base.slicc
…
MOESI_CMP_directory-dir.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
MOESI_CMP_directory-dma.sm
mem-ruby: Fixed MOESI_CMP_directory resource tracking
2020-05-06 14:42:33 +00:00
MOESI_CMP_directory-L1cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MOESI_CMP_directory-L2cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MOESI_CMP_directory-msg.sm
mem-ruby: fix MOESI_CMP_directory functional reads
2020-05-06 14:42:33 +00:00
MOESI_CMP_directory.slicc
…
MOESI_CMP_token-dir.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
MOESI_CMP_token-dma.sm
…
MOESI_CMP_token-L1cache.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_CMP_token-L2cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MOESI_CMP_token-msg.sm
…
MOESI_CMP_token.slicc
…
MOESI_hammer-cache.sm
mem-ruby: Move CacheMemory stats used in SLICC to a Stats group
2020-12-22 09:52:36 +00:00
MOESI_hammer-dir.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
MOESI_hammer-dma.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_hammer-msg.sm
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
MOESI_hammer.slicc
…
RubySlicc_ComponentMapping.sm
…
RubySlicc_Defines.sm
mem-ruby: Switch to dequeueMemRspQueue() in all Ruby protocols
2023-07-07 10:17:54 +00:00
RubySlicc_Exports.sm
mem: Atomic ops to same address
2023-08-23 14:45:25 -05:00
RubySlicc_interfaces.slicc
…
RubySlicc_MemControl.sm
gpu-compute,mem-ruby: Add support for GPU cache bypassing
2023-01-03 21:19:24 +00:00
RubySlicc_Types.sm
gpu-compute,mem-ruby: Add support for GPU cache bypassing
2023-01-03 21:19:24 +00:00
RubySlicc_Util.sm
mem-ruby: intToTick helper
2021-02-12 20:31:38 +00:00
SConscript
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
SConsopts
scons: Don't accumulate SLICC_INCLUDES.
2022-03-24 22:09:09 +00:00