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Ivan Fernandez 1e743fd85a arch-riscv: adding vector unit-stride segment stores to RISC-V (#913) 
This commit adds support for vector unit-stride segment store operations
for RISC-V (vssegXeXX). This implementation is based in two types of
microops:
- VsSegIntrlv microops that properly interleave source registers into
structs.
- VsSeg microops that store data in memory as contiguous structs of
several fields.

Change-Id: Id80dd4e781743a60eb76c18b6a28061f8e9f723d

Gem5 issue: https://github.com/gem5/gem5/issues/382
2024-03-22 15:45:58 -07:00
..
checker
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
kvm
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
minor
arch-riscv: adding vector unit-stride segment loads to RISC-V (#851)
2024-03-06 11:27:06 -08:00
o3
cpu-o3, arch: Fix SMT bug arising from v23.0 and make gem5 more robust with SMT (#828)
2024-02-19 08:52:31 +00:00
pred
misc,python: Add isort hook to pre-commit (#431)
2023-11-30 09:54:12 +00:00
probes
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
simple
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
testers
cpu,stdlib: Updating strided generator (#762)
2024-02-01 09:08:42 -08:00
trace
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
activity.cc
misc: Fix 'unused variable' clang errors with gem5.fast
2023-05-08 22:54:06 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
base: Add encapsulation to the loader::Symbol class
2023-12-01 22:00:26 +00:00
base.hh
cpu,mem,dev: Use Addr for cacheLineSize
2023-09-20 14:16:46 -07:00
BaseCPU.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
capstone.cc
cpu: Implement a CapstoneDisassembler
2023-10-20 09:27:51 +01:00
capstone.hh
cpu: Implement a CapstoneDisassembler
2023-10-20 09:27:51 +01:00
Capstone.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
CheckerCPU.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
cluster.hh
cpu: Formalize a CPU cluster class in the gem5 standard library
2023-01-13 12:07:51 +00:00
CpuCluster.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
CPUTracers.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
decode_cache.hh
cpu: Remove the DecodeCache namespace
2023-01-17 09:16:20 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
exec_context.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
exetrace.cc
base: Add encapsulation to the loader::Symbol class
2023-12-01 22:00:26 +00:00
exetrace.hh
cpu: Pass a reference of the parent tracer to the ExeTracerRecord
2023-10-20 09:27:50 +01:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
arch-riscv: adding vector unit-stride segment stores to RISC-V (#913)
2024-03-22 15:45:58 -07:00
inst_pb_trace.cc
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
inst_pb_trace.hh
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
inst_res.hh
cpu: Simplify and revamp the InstResult class.
2022-08-02 12:44:16 +00:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
inteltrace.cc
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
inteltrace.hh
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
Kconfig
arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)
2023-12-03 13:22:11 -08:00
nativetrace.cc
cpu: Pass a reference of the parent tracer to the ExeTracerRecord
2023-10-20 09:27:50 +01:00
nativetrace.hh
cpu: Pass a reference of the parent tracer to the ExeTracerRecord
2023-10-20 09:27:50 +01:00
nop_static_inst.cc
misc: Replace namespace Trace with lowercase trace
2022-10-02 16:30:15 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
arch-riscv: adding vector unit-stride segment stores to RISC-V (#913)
2024-03-22 15:45:58 -07:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
base: Add encapsulation to the loader::Symbol class
2023-12-01 22:00:26 +00:00
profile.hh
base: Remove the Loader namespace
2023-01-17 09:16:20 +00:00
reg_class.cc
cpu,arch: Put the name of the RegClass into the RegClass.
2022-07-29 19:30:51 +00:00
reg_class.hh
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
regfile.hh
cpu: Use arrays and abstraction to handle regs in SimpleThread.
2022-02-24 00:10:17 +00:00
SConscript
arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)
2023-12-03 13:22:11 -08:00
SConsopts
cpu: Implement a CapstoneDisassembler
2023-10-20 09:27:51 +01:00
simple_thread.cc
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
simple_thread.hh
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
cpu: Add a StaticInst::advancePC which takes a ThreadContext.
2021-12-03 03:05:41 +00:00
static_inst.hh
cpu: Add a IsPseudo StaticInstFlag for gem5 pseudo-ops
2023-10-16 13:41:04 +01:00
StaticInstFlags.py
cpu: Add a IsPseudo StaticInstFlag for gem5 pseudo-ops
2023-10-16 13:41:04 +01:00
thread_context.cc
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
thread_context.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
cpu: Merge TimingExprSrcReg and TimingExprReadIntReg.
2022-06-24 11:26:51 +00:00
timing_expr.hh
cpu: Merge TimingExprSrcReg and TimingExprReadIntReg.
2022-06-24 11:26:51 +00:00
TimingExpr.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
translation.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00