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c99d192690f2bd4bd9aec6b6ae717b949c9409ec
gem5/src/arch/x86
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Gabe Black ecd3cc85f0 arch,cpu: Use PCStateBase in StaticInst::branchTarget 
Change-Id: I1b8a2ea088b52252601968b1b1083ed712a5bfd6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52045
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-11-23 07:45:29 +00:00
..
bios
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
insts
arch,cpu: Use PCStateBase in StaticInst::branchTarget
2021-11-23 07:45:29 +00:00
isa
arch,cpu: Use PCStateBase in StaticInst::branchTarget
2021-11-23 07:45:29 +00:00
kvm
cpu-kvm,arch-x86,arch-arm,dev: Pair operator new with operator delete.
2021-11-04 04:39:24 +00:00
linux
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
regs
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
cpuid.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cpuid.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder_tables.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
emulenv.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
emulenv.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
faults.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
faults.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
fs_workload.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fs_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
interrupts.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intmessage.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa.cc
misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
2021-07-24 21:57:04 +00:00
isa.hh
arch: Add a newPCState method to the ISA class.
2021-11-23 07:45:29 +00:00
ldstflags.hh
x86,mem: Replace the x86 StoreCheck flag with READ_MODIFY_WRITE.
2021-09-05 05:29:27 +00:00
memhelpers.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
microcode_rom.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
nativetrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nativetrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable_walker.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch: Add a "set" function to set one PCState to another.
2021-11-23 07:45:29 +00:00
process.cc
misc: Move MemPool based calls to the SEWorkload.
2021-09-21 02:05:32 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pseudo_inst_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
remote_gdb.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
remote_gdb.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SConscript
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
tlb.cc
x86,mem: Replace the x86 StoreCheck flag with READ_MODIFY_WRITE.
2021-09-05 05:29:27 +00:00
tlb.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
types.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
types.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vecregs.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
x86_traits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86FsWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86ISA.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86LocalApic.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86MMU.py
arch: Add TypeTLB Param in BaseTLB
2021-07-28 08:13:09 +00:00
X86NativeTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86SeWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86TLB.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00