Yu-hsin Wang 76046ee3ce fastmodel: CortexR52 support gdb ...

We change several things to support basic gdb.

1. Correct the memory translation.
memory_getUsefulAddressTranslations returns an empty list. So there's no
memory translation in R52.

2. Implement FPSCR for gdb collecting status.

3. Correct the breakpoint memory space.

Change-Id: Icc824502faec5ac228003f0de7e9dbe26babe7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52623
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-11-11 01:32:16 +00:00

..

amdgpu

arch-gcn3,arch-vega: Don't write exec in v_cmp_f_i32

2021-11-05 19:52:40 +00:00

arm

fastmodel: CortexR52 support gdb

2021-11-11 01:32:16 +00:00

gcn3

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

generic

arch,cpu: Refactor PCState construction a little.

2021-11-08 02:16:01 +00:00

isa_parser

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

mips

arch: Make the MMU ranged translateFunction pure virtual.

2021-10-22 21:43:02 +00:00

null

arch,cpu,mem,sim: Fold arch/locked_mem.hh into the BaseISA class.

2021-09-28 19:56:01 +00:00

power

arch,cpu: Refactor PCState construction a little.

2021-11-08 02:16:01 +00:00

riscv

arch-riscv: Add NMI support

2021-11-10 06:29:33 +00:00

sparc

arch: Make the MMU ranged translateFunction pure virtual.

2021-10-22 21:43:02 +00:00

x86

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm_test.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

micro_asm.py

misc: Use python 3's argumentless super().

2021-11-09 13:04:44 +00:00

SConscript

arch: Remove the page_size.hh switching header file.

2021-10-22 21:43:02 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00