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a5ab19d3ef3db2b7a012626b5b388b47dbf680b7
gem5/src/sim
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Gabe Black 9df4159456 sim: Add some helpers for working with values in buffers. 
This change adds helpers to get and set values from byte buffers of
variable size, and to print them. It also provides a helper to print a
buffer of bytes.

Change-Id: I23210505f99488a901bed244ffc70ef4736470d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57149
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-26 09:56:26 +00:00
..
guest_abi
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
power
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
probe
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
async.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
async.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
aux_vector.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
backtrace_glibc.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backtrace_none.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
backtrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
bufval.cc
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
bufval.hh
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
bufval.test.cc
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
byteswap.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
byteswap.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clock_domain.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clock_domain.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ClockDomain.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clocked_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
clocked_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ClockedObject.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
core.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
core.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
cur_tick.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cur_tick.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config_ini.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config_ini.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cxx_config.cc
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_config.hh
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_manager.cc
scons,sim: Eliminate the generated cxx_config/init.cc file.
2022-01-13 05:21:41 +00:00
cxx_manager.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
debug.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
debug.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
drain.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
drain.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dvfs_handler.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dvfs_handler.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DVFSHandler.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
emul_driver.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
eventq.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
eventq.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
faults.cc
arch,sim-se: Update the PC before emulating a system call.
2021-12-12 00:29:53 +00:00
faults.hh
misc: Include static_inst_fwd.hh in sim/faults.hh.
2021-10-01 04:57:56 +00:00
fd_array.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
fd_array.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
fd_entry.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
fd_entry.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
full_system.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
futex_map.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
futex_map.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
global_event.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
global_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
globals.test.cc
sim,tests: Add unit test for Globals
2022-02-09 10:24:54 +00:00
guest_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
guest_abi.test.cc
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
init_signals.cc
sim: fix build error when glibc >= 2.34
2021-11-25 11:49:15 +00:00
init_signals.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
init.cc
sim: Make the EmbeddedPyBind::initAll method work correctly.
2021-12-16 01:57:26 +00:00
init.hh
sim: Make the EmbeddedPyBind::initAll method work correctly.
2021-12-16 01:57:26 +00:00
insttracer.hh
sim: Fix style in insttracer.hh.
2022-02-25 08:08:32 +00:00
InstTracer.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
kernel_workload.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
kernel_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
linear_solver.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
linear_solver.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
main.cc
sim,python: Use scoped_interpreter_guard's argc and argv ctor arguments.
2021-12-17 06:58:46 +00:00
mathexpr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mathexpr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_pool.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
mem_pool.hh
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
mem_state.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_state.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
port.test.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_domain.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_domain.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
power_state.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
power_state.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
PowerDomain.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PowerState.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process_impl.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
sim: Align process memory allocations.
2021-10-11 22:05:28 +00:00
process.hh
sim: Align process memory allocations.
2021-10-11 22:05:28 +00:00
Process.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
proxy_ptr.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
proxy_ptr.test.cc
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
pseudo_inst.cc
misc: Stop using getVirtProxy.
2021-07-23 03:42:17 +00:00
pseudo_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
py_interact.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
py_interact.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
python.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
redirect_path.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
redirect_path.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
RedirectPath.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
root.cc
sim: Don't serialize a root.isa string in checkpoints.
2021-07-31 18:06:52 +00:00
root.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
Root.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SConscript
sim: Add some helpers for working with values in buffers.
2022-02-26 09:56:26 +00:00
SConsopts
scons: Convert gem5_scons.Configure to a context manager.
2021-04-13 01:04:54 +00:00
se_signal.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
se_signal.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
se_workload.cc
sim: Move System specific code out of MemPools.
2021-09-30 00:31:10 +00:00
se_workload.hh
sim: Move the MemPools object out of System and into SEWorkload.
2021-09-30 00:30:49 +00:00
serialize_handlers.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
serialize_handlers.test.cc
sim,tests: Add unit test for sim/serialize_handlers
2021-09-22 05:31:01 +00:00
serialize.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
serialize.hh
sim: Explicitly specify the namespace of serialization helpers.
2021-08-28 04:18:12 +00:00
serialize.test.cc
sim,tests: Add unit test for sim/serialize.hh
2021-09-22 05:31:01 +00:00
sim_events.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_events.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_exit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sim_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
simulate.cc
sim: Fix hang while terminating threads with fork
2021-09-21 15:08:15 +00:00
simulate.hh
sim: Fix fork for multithreaded simulations
2021-09-19 17:32:59 +00:00
stat_control.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stat_control.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
stat_register.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stat_register.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stats.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stats.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sub_system.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sub_system.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SubSystem.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
syscall_abi.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
syscall_debug_macros.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_desc.cc
sim-se: (Re)add support for retrying system calls.
2021-12-17 05:45:26 +00:00
syscall_desc.hh
sim-se: (Re)add support for retrying system calls.
2021-12-17 05:45:26 +00:00
syscall_emul_buf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
syscall_emul.cc
sim-se: Implement mknodat syscall
2021-10-20 15:10:45 +00:00
syscall_emul.hh
arch,sim-se: Update the PC before emulating a system call.
2021-12-12 00:29:53 +00:00
syscall_return.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
system.cc
cpu-kvm,sim: Reverse the relationship between System and KvmVM.
2022-02-04 12:11:32 +00:00
system.hh
cpu-kvm,sim: Reverse the relationship between System and KvmVM.
2022-02-04 12:11:32 +00:00
System.py
cpu-kvm,sim: Reverse the relationship between System and KvmVM.
2022-02-04 12:11:32 +00:00
ticked_object.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
ticked_object.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TickedObject.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vma.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vma.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
voltage_domain.cc
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
voltage_domain.hh
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
VoltageDomain.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
workload.cc
base: Only trap to GDB if remote GDB is connected
2021-10-04 18:59:14 +00:00
workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
Workload.py
sim: Remove some old transitional code in SEWorkload.
2021-11-18 17:08:34 +00:00