Gabe Black a5ab19d3ef arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type). ...

Change-Id: I32be58cce831c8c7d5b9e3d3f49f428a06c722a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49713
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-03-01 01:36:07 +00:00

..

arch

arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).

2022-03-01 01:36:07 +00:00

base

scons: Use env and not main in SConscripts.

2022-02-25 09:32:14 +00:00

cpu

arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).

2022-03-01 01:36:07 +00:00

dev

dev,arch-x86: Add an x86/compatibility IDE controller.

2022-02-26 01:59:50 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

gpu-compute: Fix register checking and allocation in dyn manager

2022-02-18 18:46:33 +00:00

kern

sim-se: Add additional TGT_AT_* constants for Linux.

2021-11-24 22:48:17 +00:00

learning_gem5

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

mem

mem-cache: Fix unit inconsistencies in base cache stats

2022-02-27 23:01:03 +00:00

proto

sim,misc: Move protobuf housekeeping out of gem5Main.

2021-12-08 08:01:23 +00:00

python

python: Update gem5 url output by the simulator

2022-02-14 21:14:26 +00:00

sim

sim: Add some helpers for working with values in buffers.

2022-02-26 09:56:26 +00:00

sst

scons: Add sim_object and enums arguments to SimObject().

2021-12-08 08:01:23 +00:00

systemc

scons: Use env and not main in SConscripts.

2022-02-25 09:32:14 +00:00

Doxyfile

misc: Revert v21.2 specific commits for develop

2021-12-28 21:30:21 +00:00

SConscript

scons: Handle TARGET_GPU_ISA not being set.

2022-02-23 02:31:56 +00:00