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Adrian Herrera 0e8ce8b12e sim: kernelExtras if no kernel provided 
kernelExtras facilitates a way for users to provide additional
blobs to load into memory. As of now, the creation of the extra
images is done independently of the kernel being provided, but
the loading is only done if the kernel is present.

This patch refactors the loading of extra images to be committed
if no kernel is present.

Change-Id: I900542e1034ade8d757d01823cfd4a30f0b36734
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22850
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-12-16 10:33:56 +00:00
..
power
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
probe
mem: Record the request master ID in the PacketInfo structure.
2017-09-25 21:13:24 +00:00
arguments.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
arguments.hh
arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.
2019-05-30 06:07:33 +00:00
async.cc
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
async.hh
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
aux_vector.hh
arch, sim: Simplify the AuxVector type.
2019-04-28 05:16:01 +00:00
backtrace_glibc.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
backtrace_none.cc
sim: Add support for generating back traces on errors
2015-12-04 00:12:58 +00:00
backtrace.hh
sim: Add support for generating back traces on errors
2015-12-04 00:12:58 +00:00
byteswap.hh
arch: Get rid of the (Big|Little)EndianGuest namespaces.
2019-11-18 20:02:31 +00:00
byteswap.test.cc
base: Remove tests making use of Big/LittleEndianOrder Namespace
2019-11-21 09:19:16 +00:00
clock_domain.cc
sim: Convert power modelling framework to new-style stats
2019-09-26 13:22:55 +00:00
clock_domain.hh
sim: Convert power modelling framework to new-style stats
2019-09-26 13:22:55 +00:00
ClockDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
clocked_object.cc
sim: Convert power modelling framework to new-style stats
2019-09-26 13:22:55 +00:00
clocked_object.hh
sim: Convert power modelling framework to new-style stats
2019-09-26 13:22:55 +00:00
ClockedObject.py
pwr: Enable multiple power models per component
2017-11-16 16:15:12 +00:00
core.cc
sim: Push the global frequency management code into C++.
2018-11-12 22:05:00 +00:00
core.hh
sim: Push the global frequency management code into C++.
2018-11-12 22:05:00 +00:00
cxx_config_ini.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
cxx_config_ini.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
cxx_config.cc
config: Add the ability to read a config file using C++ and Python
2014-10-16 05:49:37 -04:00
cxx_config.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
cxx_manager.cc
mem: Minimize the use of MemObject.
2019-04-28 01:19:40 +00:00
cxx_manager.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
debug.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
debug.hh
sim: Add relative break scheduling
2015-10-09 14:27:09 -05:00
drain.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
drain.hh
base, sim, dev: Remove SWIG
2017-05-02 12:37:32 +00:00
dvfs_handler.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
dvfs_handler.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
DVFSHandler.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
emul_driver.hh
sim-se: change syscall function signature
2019-05-21 20:42:38 +00:00
eventq_impl.hh
sim: Add hooks to implement event reference counting
2017-05-24 14:28:45 +00:00
eventq.cc
sim: prefix --debug-flags Event logs with the flag name
2019-11-26 12:46:59 +00:00
eventq.hh
cpu: fixed how O3 CPU executes an exit system call
2019-02-08 15:18:22 +00:00
faults.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
faults.hh
sim: Add getter to fault virtual address
2019-07-18 15:09:22 +00:00
fd_array.cc
sim-se: create Proc out files in out dir
2019-04-29 20:37:29 +00:00
fd_array.hh
syscall_emul: style changes and FDArray refactor
2018-09-19 20:53:13 +00:00
fd_entry.cc
style: fix amd license and style issues
2018-05-16 15:32:01 +00:00
fd_entry.hh
sim-se: add eventfd system call
2019-05-03 15:55:16 +00:00
full_system.hh
…
futex_map.hh
sim-se: don't wake up threads that are halted on futex
2019-11-25 12:02:11 +00:00
global_event.cc
sim: Fix resource leak in BaseGlobalEvent
2014-09-09 04:36:32 -04:00
global_event.hh
dev: Distributed Ethernet link for distributed gem5 simulations
2016-01-07 16:33:47 -06:00
guest_abi.hh
sim: Add a mechanism to translate ABIs to call host funcs from a TC.
2019-12-10 23:58:14 +00:00
init_signals.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
init_signals.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
init.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
init.hh
python: Fix native module initialisation on Python 3
2019-02-12 09:38:12 +00:00
initparam_keys.hh
dev: Distributed Ethernet link for distributed gem5 simulations
2016-01-07 16:33:47 -06:00
insttracer.hh
arch,cpu: Add vector predicate registers
2019-01-30 16:57:54 +00:00
InstTracer.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
linear_solver.cc
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
linear_solver.hh
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
main.cc
python: Fix native module initialisation on Python 3
2019-02-12 09:38:12 +00:00
mathexpr.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
mathexpr.hh
sim: Added library include to fix build errors on clang-703.0.31
2016-06-20 15:34:41 +01:00
mem_state.hh
sim: Fix need to save address space info during serialization.
2017-11-21 16:35:54 +00:00
microcode_rom.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
microcode_rom.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
port.cc
mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly.
2019-08-27 22:17:45 +00:00
port.hh
sim: Add a << overload for the Port class which prints its name.
2019-08-27 22:18:10 +00:00
process_impl.hh
arch,sim: Make copyStringArray take an explicit endianness.
2019-10-30 22:29:23 +00:00
process.cc
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
process.hh
arch,cpu,sim: Push syscall number determination up to processes.
2019-12-10 23:58:14 +00:00
Process.py
sim-se: add a release parameter to Process.py
2019-05-29 09:34:37 +00:00
pseudo_inst.cc
sim,arch: Collapse the ISA specific versions of m5Syscall.
2019-12-10 23:58:14 +00:00
pseudo_inst.hh
sim,arch: Collapse the ISA specific versions of m5Syscall.
2019-12-10 23:58:14 +00:00
py_interact.cc
style: Force Python.h to be included before main header
2017-02-07 15:28:33 +00:00
py_interact.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
python.cc
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
2019-03-19 10:22:50 +00:00
redirect_path.cc
sim-se: add a faux-filesystem
2019-04-25 18:11:34 +00:00
redirect_path.hh
sim-se: add a faux-filesystem
2019-04-25 18:11:34 +00:00
RedirectPath.py
sim-se: add a faux-filesystem
2019-04-25 18:11:34 +00:00
root.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
root.hh
sim: Stop using loadState in the Root SimObject.
2017-09-21 17:34:59 +00:00
Root.py
sim: Remove redundant buildEnv import
2016-12-19 16:25:37 +00:00
SConscript
tests: Added GTests for byteswap.hh
2019-11-16 07:25:58 +00:00
se_signal.cc
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
se_signal.hh
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
serialize.cc
sim: Move paramIn/Out definition to header file
2018-11-14 10:13:01 +00:00
serialize.hh
sim: Add size to array unserialization error message
2019-03-12 14:20:50 +00:00
sim_events.cc
sim: Add a mechanism to exit the simulation loop immediately.
2019-02-19 23:34:05 +00:00
sim_events.hh
sim: Add a mechanism to exit the simulation loop immediately.
2019-02-19 23:34:05 +00:00
sim_exit.hh
sim: Add a mechanism to exit the simulation loop immediately.
2019-02-19 23:34:05 +00:00
sim_object.cc
stats: Add support for hierarchical stats
2019-08-29 09:01:38 +00:00
sim_object.hh
stats: Add support for hierarchical stats
2019-08-29 09:01:38 +00:00
simulate.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
simulate.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
stat_control.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stat_control.hh
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stat_register.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
stat_register.hh
base, sim, dev: Remove SWIG
2017-05-02 12:37:32 +00:00
stats.hh
…
sub_system.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
sub_system.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
SubSystem.py
arm: DT autogeneration - Device Tree generation methods
2018-01-29 22:21:30 +00:00
syscall_debug_macros.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_desc.cc
sim: Get rid of the now unused SyscallDesc flags and methods.
2019-12-10 23:58:14 +00:00
syscall_desc.hh
sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.
2019-12-10 23:58:14 +00:00
syscall_emul_buf.hh
arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.
2019-05-30 14:20:03 +00:00
syscall_emul.cc
sim: Reintroduce the ignoreWarnOnceFunc syscall handler.
2019-12-10 23:58:14 +00:00
syscall_emul.hh
sim: Reintroduce the ignoreWarnOnceFunc syscall handler.
2019-12-10 23:58:14 +00:00
syscall_return.hh
sim: Add a suppression mechanism to the SyscallReturn class.
2019-12-04 04:29:50 +00:00
system.cc
sim: kernelExtras if no kernel provided
2019-12-16 10:33:56 +00:00
system.hh
sim: Add a getGuestByteOrder accessor to the system class.
2019-10-30 22:29:23 +00:00
System.py
mem: Minimize the use of MemObject.
2019-04-28 01:19:40 +00:00
ticked_object.cc
sim, gdb: Refactor some Event subclasses into lambdas
2017-07-12 20:07:05 +00:00
ticked_object.hh
sim, gdb: Refactor some Event subclasses into lambdas
2017-07-12 20:07:05 +00:00
TickedObject.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
voltage_domain.cc
sim: Convert power modelling framework to new-style stats
2019-09-26 13:22:55 +00:00
voltage_domain.hh
sim: Convert power modelling framework to new-style stats
2019-09-26 13:22:55 +00:00
VoltageDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
vptr.hh
arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.
2019-05-30 14:20:03 +00:00