arch: Get rid of the (Big|Little)EndianGuest namespaces.

These namespaces were used to set up an environment/context where there
was an implicit guest namespace. This is an issue when there may be
multiple guest endiannesses which might be different. In cases where
we don't know what the guest endianness is, we can't rely on it being
an implicit part of our context since that would be ambiguous. In cases
where we do know, for instance in ISA specific code, we can just use
the endianness specific version that's appropriate for that context.

This also (somewhat) removes the assumption that there is a single
endianness that applies for a particular ISA. Practically speaking this
assumption will probably still stand though, since there would likely
be a non-trivial performance penalty to apply a configurable endianness
instead of a fixed one the compiler can optomize/remove.

Change-Id: I2dff338b58726d724f387388efe32d9233885680
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/alpha/isa_traits.hh

@@ -32,8 +32,6 @@
 #ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
 #define __ARCH_ALPHA_ISA_TRAITS_HH__
 
-namespace LittleEndianGuest {}
-
 #include "arch/alpha/ipr.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
@@ -41,7 +39,7 @@ namespace LittleEndianGuest {}
 
 namespace AlphaISA {
 
-using namespace LittleEndianGuest;
+const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
 StaticInstPtr decodeInst(ExtMachInst);
 

src/arch/arm/isa_traits.hh

@@ -49,11 +49,9 @@
 #include "base/types.hh"
 #include "cpu/static_inst_fwd.hh"
 
-namespace LittleEndianGuest {}
-
 namespace ArmISA
 {
-    using namespace LittleEndianGuest;
+    const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
     StaticInstPtr decodeInst(ExtMachInst);
 

src/arch/mips/isa_traits.hh

@@ -38,12 +38,10 @@
 #include "base/types.hh"
 #include "cpu/static_inst_fwd.hh"
 
-namespace LittleEndianGuest {}
-
 namespace MipsISA
 {
 
-using namespace LittleEndianGuest;
+const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
 StaticInstPtr decodeInst(ExtMachInst);
 

src/arch/mips/system.cc

@@ -41,8 +41,6 @@
 #include "params/MipsSystem.hh"
 #include "sim/byteswap.hh"
 
-using namespace LittleEndianGuest;
-
 MipsSystem::MipsSystem(Params *p) : System(p)
 {
 }

src/arch/power/isa_traits.hh

@@ -39,12 +39,10 @@
 #include "base/types.hh"
 #include "cpu/static_inst_fwd.hh"
 
-namespace BigEndianGuest {}
-
 namespace PowerISA
 {
 
-using namespace BigEndianGuest;
+const ByteOrder GuestByteOrder = BigEndianByteOrder;
 
 StaticInstPtr decodeInst(ExtMachInst);
 

src/arch/riscv/isa_traits.hh

@@ -50,12 +50,10 @@
 #include "base/types.hh"
 #include "cpu/static_inst_fwd.hh"
 
-namespace LittleEndianGuest {}
-
 namespace RiscvISA
 {
 
-using namespace LittleEndianGuest;
+const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;

src/arch/riscv/system.cc

@@ -42,8 +42,6 @@
 #include "params/RiscvSystem.hh"
 #include "sim/byteswap.hh"
 
-using namespace LittleEndianGuest;
-
 RiscvSystem::RiscvSystem(Params *p)
     : System(p),
       _isBareMetal(p->bare_metal),

src/arch/sparc/isa_traits.hh

@@ -37,12 +37,10 @@
 #include "base/types.hh"
 #include "cpu/static_inst_fwd.hh"
 
-namespace BigEndianGuest {}
-
 namespace SparcISA
 {
-// This makes sure the big endian versions of certain functions are used.
-using namespace BigEndianGuest;
+
+const ByteOrder GuestByteOrder = BigEndianByteOrder;
 
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;

src/arch/sparc/system.cc

@@ -38,8 +38,6 @@
 #include "params/SparcSystem.hh"
 #include "sim/byteswap.hh"
 
-using namespace BigEndianGuest;
-
 namespace
 {
 

src/arch/x86/isa_traits.hh

@@ -45,13 +45,9 @@
 #include "base/compiler.hh"
 #include "base/types.hh"
 
-namespace LittleEndianGuest {}
-
 namespace X86ISA
 {
-    //This makes sure the little endian version of certain functions
-    //are used.
-    using namespace LittleEndianGuest;
+    const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;

src/arch/x86/linux/system.cc

@@ -48,7 +48,6 @@
 #include "params/LinuxX86System.hh"
 #include "sim/byteswap.hh"
 
-using namespace LittleEndianGuest;
 using namespace X86ISA;
 
 LinuxX86System::LinuxX86System(Params *p)

src/arch/x86/system.cc

@@ -48,7 +48,6 @@
 #include "cpu/thread_context.hh"
 #include "params/X86System.hh"
 
-using namespace LittleEndianGuest;
 using namespace X86ISA;
 
 X86System::X86System(Params *p) :

src/sim/byteswap.hh

@@ -169,37 +169,4 @@ inline T gtoh(T value, ByteOrder guest_byte_order)
         betoh(value) : letoh(value);
 }
 
-namespace BigEndianGuest
-{
-    const ByteOrder GuestByteOrder = BigEndianByteOrder;
-    template <typename T>
-    inline T gtole(T value) {return betole(value);}
-    template <typename T>
-    inline T letog(T value) {return letobe(value);}
-    template <typename T>
-    inline T gtobe(T value) {return value;}
-    template <typename T>
-    inline T betog(T value) {return value;}
-    template <typename T>
-    inline T htog(T value) {return htobe(value);}
-    template <typename T>
-    inline T gtoh(T value) {return betoh(value);}
-}
-
-namespace LittleEndianGuest
-{
-    const ByteOrder GuestByteOrder = LittleEndianByteOrder;
-    template <typename T>
-    inline T gtole(T value) {return value;}
-    template <typename T>
-    inline T letog(T value) {return value;}
-    template <typename T>
-    inline T gtobe(T value) {return letobe(value);}
-    template <typename T>
-    inline T betog(T value) {return betole(value);}
-    template <typename T>
-    inline T htog(T value) {return htole(value);}
-    template <typename T>
-    inline T gtoh(T value) {return letoh(value);}
-}
 #endif // __SIM_BYTE_SWAP_HH__