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967bada8db0e677a135f73bae417fd3d03fb6cb0
gem5/src/cpu
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Gabe Black 967bada8db arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array. 
The array is indexed using the register class.

Change-Id: I6cfd9735afa03e386e01e9e255fd6e55b7ba7272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49712
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-01 01:36:07 +00:00
..
checker
cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.
2022-02-19 20:23:51 +00:00
kvm
cpu-kvm,sim: Reverse the relationship between System and KvmVM.
2022-02-04 12:11:32 +00:00
minor
cpu-simple: Ignore writes to the "zero" register.
2022-02-26 05:02:35 +00:00
o3
cpu,arch-arm: Use a sentry class valid for invalid RegIds.
2022-02-28 22:04:27 +00:00
pred
cpu: Remove an unused variable from one of the branch predictors.
2022-02-26 13:06:07 +00:00
simple
cpu-simple: Ignore writes to the "zero" register.
2022-02-26 05:02:35 +00:00
testers
cpu: fix issues with ruby's memtest
2022-02-17 20:43:08 +00:00
trace
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
activity.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
arch,cpu: Stop using and remove ThreadContext::instAddr.
2021-11-30 23:30:06 +00:00
base.hh
cpu: Create a virtual BaseCPU::htmSendAbortSignal method.
2021-10-26 19:16:58 +00:00
BaseCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
CheckerCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CPUTracers.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decode_cache.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
exec_context.hh
cpu,arch: Turn the read|set*Operand methods into get/setRegOperand.
2022-02-19 20:23:51 +00:00
exetrace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
exetrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_pb_trace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
inst_pb_trace.hh
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
inst_res.hh
cpu: Generalize the vec reg types out of InstResult.
2021-09-09 16:03:18 +00:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
inteltrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
nativetrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nativetrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
nop_static_inst.cc
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
reg_class.cc
misc: Use the new bufval helpers in RegClass and Packet.
2022-02-26 09:56:26 +00:00
reg_class.hh
cpu,arch-arm: Use a sentry class valid for invalid RegIds.
2022-02-28 22:04:27 +00:00
regfile.hh
cpu: Use arrays and abstraction to handle regs in SimpleThread.
2022-02-24 00:10:17 +00:00
SConscript
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
simple_thread.cc
cpu: Use arrays and abstraction to handle regs in SimpleThread.
2022-02-24 00:10:17 +00:00
simple_thread.hh
cpu-simple: Ignore writes to the "zero" register.
2022-02-26 05:02:35 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
cpu: Add a StaticInst::advancePC which takes a ThreadContext.
2021-12-03 03:05:41 +00:00
static_inst.hh
arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array.
2022-03-01 01:36:07 +00:00
StaticInstFlags.py
arch,cpu: Get rid of the IsMemRef StaticInst flag.
2020-09-16 12:13:08 +00:00
thread_context.cc
cpu: Remove VecRegContainer from ThreadContext::compare.
2022-02-24 23:22:24 +00:00
thread_context.hh
cpu: Eliminate the (read|set)VecPredReg helpers from ThreadContext.
2022-02-24 00:10:17 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingExpr.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translation.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00