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9235ae56c282d5a02ada3ed9b4e0fe2ee5738bde
gem5/src/cpu/o3
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Nikos Nikoleris 9235ae56c2 cpu: Fix checker cpu instantiation 
This change uses the params as instantiated from the default
constructor to create the checker cpu. If any of these parameters are
invalid for the checker cpu, the simulation will exit with a warning.

Change-Id: I0e58ed096c9ea5f413f2e9b64d8d184d9b0fc84e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21079
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-24 13:24:55 +00:00
..
probe
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
base_dyn_inst.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
checker.cc
cpu: Fix checker cpu instantiation
2019-09-24 13:24:55 +00:00
checker.hh
cpu: Add header files for checker CPUs
2012-11-02 11:32:01 -05:00
comm.hh
cpu: Refactor of Physical Register implementation
2019-03-14 15:09:07 +00:00
commit_impl.hh
misc: Removed inconsistency in O3* debug msgs
2019-04-03 16:50:22 +00:00
commit.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
commit.hh
cpu: support atomic memory request type with AtomicOpFunctor
2019-02-08 15:27:04 +00:00
cpu_policy.hh
cpu/o3: clean up rename map and free list
2013-10-15 14:22:44 -04:00
cpu.cc
cpu: Move the instruction port into o3's fetch stage.
2019-08-28 02:14:53 +00:00
cpu.hh
cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>
2019-09-23 12:32:08 +00:00
decode_impl.hh
misc: Removed inconsistency in O3* debug msgs
2019-04-03 16:50:22 +00:00
decode.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
decode.hh
cpu: fixed how O3 CPU executes an exit system call
2019-02-08 15:18:22 +00:00
dep_graph.hh
cpu: Change raw pointers to STL Containers
2018-12-03 14:23:56 +00:00
deriv.cc
cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum
2019-01-17 11:09:08 +00:00
deriv.hh
cpu: O3 add a header declaring the DerivO3CPU
2012-11-02 11:32:01 -05:00
dyn_inst_impl.hh
cpu: alpha: Delete all occurrances of the simPalCheck function.
2019-04-30 07:37:51 +00:00
dyn_inst.cc
O3: Generaize the O3 IMPL class so it isn't split out by ISA.
2008-10-09 00:10:02 -07:00
dyn_inst.hh
cpu: alpha: Delete all occurrances of the simPalCheck function.
2019-04-30 07:37:51 +00:00
fetch_impl.hh
cpu: Move the instruction port into o3's fetch stage.
2019-08-28 02:14:53 +00:00
fetch.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
fetch.hh
cpu: Move the instruction port into o3's fetch stage.
2019-08-28 02:14:53 +00:00
free_list.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
free_list.hh
cpu-o3: Add support for pinned writes
2019-05-30 15:55:59 +00:00
fu_pool.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
fu_pool.hh
cpu: Change literal integer constants to meaningful labels
2015-05-05 16:47:24 +01:00
FuncUnitConfig.py
arch-arm,cpu: Add initial support for Arm SVE
2019-03-14 10:42:27 +00:00
FUPool.py
arch-arm,cpu: Add initial support for Arm SVE
2019-03-14 10:42:27 +00:00
iew_impl.hh
cpu: Move O3's data port into the LSQ.
2019-08-28 02:14:29 +00:00
iew.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
iew.hh
cpu: fixed how O3 CPU executes an exit system call
2019-02-08 15:18:22 +00:00
impl.hh
cpu: Fix the usage of const DynInstPtr
2018-11-16 10:39:03 +00:00
inst_queue_impl.hh
cpu-o3: fix atomic instructions non-speculative
2019-08-07 17:39:51 +00:00
inst_queue.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
inst_queue.hh
cpu-o3: Make the smtIQPolicy a Param.ScopedEnum
2019-01-17 11:09:08 +00:00
isa_specific.hh
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
lsq_impl.hh
cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>
2019-09-23 12:32:08 +00:00
lsq_unit_impl.hh
cpu-o3: Fix too strict assert condition in writeback()
2019-07-28 16:28:43 +00:00
lsq_unit.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
lsq_unit.hh
cpu-o3: Set packet data type for IPR read
2019-07-13 00:48:33 +00:00
lsq.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
lsq.hh
cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>
2019-09-23 12:32:08 +00:00
mem_dep_unit_impl.hh
misc: Removed inconsistency in O3* debug msgs
2019-04-03 16:50:22 +00:00
mem_dep_unit.cc
clang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 12:05:52 -05:00
mem_dep_unit.hh
cpu: Fix the usage of const DynInstPtr
2018-11-16 10:39:03 +00:00
O3Checker.py
python: Don't assume SimObjects live in the global namespace
2019-02-12 09:43:00 +00:00
O3CPU.py
cpu-o3: Add cache read ports limit to LSQ
2019-02-22 12:16:20 +00:00
regfile.cc
cpu-o3: Add support for pinned writes
2019-05-30 15:55:59 +00:00
regfile.hh
cpu-o3: Add support for pinned writes
2019-05-30 15:55:59 +00:00
rename_impl.hh
cpu-o3: Add support for pinned writes
2019-05-30 15:55:59 +00:00
rename_map.cc
cpu-o3: Add support for pinned writes
2019-05-30 15:55:59 +00:00
rename_map.hh
arch,cpu: Add vector predicate registers
2019-01-30 16:57:54 +00:00
rename.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
rename.hh
cpu: fixed how O3 CPU executes an exit system call
2019-02-08 15:18:22 +00:00
rob_impl.hh
cpu: Added correct return type for ROB::countInsts
2019-05-29 14:38:46 +00:00
rob.cc
now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory
2006-06-30 20:49:31 -04:00
rob.hh
cpu: Added correct return type for ROB::countInsts
2019-05-29 14:38:46 +00:00
SConscript
cpu: Remove Ozone CPU from the source tree
2014-10-09 17:51:58 -04:00
SConsopts
arch, cpu: Factor out the ExecContext into a proper base class
2014-09-03 07:42:22 -04:00
scoreboard.cc
cpu: Physical register structural + flat indexing
2017-07-05 14:43:49 +00:00
scoreboard.hh
cpu-o3: Add M5_VAR_USED to variable
2017-10-19 23:03:58 +00:00
store_set.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
store_set.hh
LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
2011-08-19 15:08:07 -05:00
thread_context_impl.hh
cpu, sim: Return PortProxy &s from all the proxy accessors.
2019-05-30 14:20:03 +00:00
thread_context.cc
style: change C/C++ source permissions to noexec
2018-01-10 16:49:23 +00:00
thread_context.hh
arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.
2019-05-30 14:20:03 +00:00
thread_state.hh
syscall_emul: [patch 13/22] add system call retry capability
2015-07-20 09:15:21 -05:00