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87c2f36fa831b9530f4ad0ff7f8f2d91ae534de6
gem5/src/cpu
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Giacomo Travaglini 87c2f36fa8 cpu: Fix InvalidRegClass access in CheckerCPU 
This is fixing long regressions:

https://jenkins.gem5.org/job/nightly/252/console

Change-Id: Ica56b950e5091d3357060f566e02195cc8136924
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60449
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-06-08 21:58:27 +00:00
..
checker
cpu: Fix InvalidRegClass access in CheckerCPU
2022-06-08 21:58:27 +00:00
kvm
arch-arm,cpu: Move KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check to Kvm
2022-05-03 17:09:05 +00:00
minor
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
o3
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
pred
cpu: nullptr in a DPRINTF statement
2022-04-28 16:57:59 +00:00
simple
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
testers
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
trace
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
activity.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
activity.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
base.cc
cpu,sim: Don't tie ThreadContext contextId to the CPU ID.
2022-03-01 02:55:20 +00:00
base.hh
cpu: Create a virtual BaseCPU::htmSendAbortSignal method.
2021-10-26 19:16:58 +00:00
BaseCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
CheckerCPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
CPUTracers.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decode_cache.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dummy_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
DummyChecker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
exec_context.hh
cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd
2022-04-05 09:24:16 +00:00
exetrace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
exetrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
func_unit.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
func_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnit.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_pb_trace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
inst_pb_trace.hh
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
inst_res.hh
cpu: Generalize the vec reg types out of InstResult.
2021-09-09 16:03:18 +00:00
inst_seq.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
InstPBTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inteltrace.cc
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
inteltrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
nativetrace.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
nativetrace.hh
arch,cpu,sim: Use PCState * and & to trace and not TheISA::PCState.
2021-11-23 07:45:29 +00:00
nop_static_inst.cc
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
nop_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
null_static_inst.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
op_class.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pc_event.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
pc_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
profile.hh
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
reg_class.cc
misc: Use the new bufval helpers in RegClass and Packet.
2022-02-26 09:56:26 +00:00
reg_class.hh
cpu: constexpr most of RegId's methods, and add a RegIndex operator.
2022-06-08 07:07:53 +00:00
regfile.hh
cpu: Use arrays and abstraction to handle regs in SimpleThread.
2022-02-24 00:10:17 +00:00
SConscript
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
simple_thread.cc
cpu: Use arrays and abstraction to handle regs in SimpleThread.
2022-02-24 00:10:17 +00:00
simple_thread.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
smt.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst_fwd.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
static_inst.cc
cpu: Add a StaticInst::advancePC which takes a ThreadContext.
2021-12-03 03:05:41 +00:00
static_inst.hh
cpu: Fix build for MacOS.
2022-03-23 13:58:28 +00:00
StaticInstFlags.py
arch,cpu: Get rid of the IsMemRef StaticInst flag.
2020-09-16 12:13:08 +00:00
thread_context.cc
cpu: Remove VecRegContainer from ThreadContext::compare.
2022-02-24 23:22:24 +00:00
thread_context.hh
cpu: Make getIsaPtr const.
2022-03-03 19:39:26 +00:00
thread_state.cc
fastmodel,cpu: Eliminate the unused getVirtProxy.
2021-07-23 08:59:36 +00:00
thread_state.hh
cpu,fastmodel: Eliminate the now unnecessary initMemProxies method.
2021-07-23 08:59:54 +00:00
timebuf.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
timing_expr.cc
cpu: Fix style in cpu/timing_expr.cc.
2022-06-08 20:36:07 +00:00
timing_expr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingExpr.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translation.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
utils.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00