Swapnil Haria 83f2b25398 arch-x86: Adding clflush, clflushopt, clwb instructions ...

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

2018-01-23 22:17:46 +00:00

..

arch

arch-x86: Adding clflush, clflushopt, clwb instructions

2018-01-23 22:17:46 +00:00

base

base: Hide the BitUnion::__StorageType type.

2018-01-20 07:31:50 +00:00

cpu

sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().

2018-01-12 00:57:56 +00:00

dev

base: Rework bitunions so they can be more flexible.

2018-01-20 07:29:24 +00:00

doc

sim: Adding support for power models

2016-06-06 17:16:44 +01:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

tarch, mem: Abstract the data stored in the SE page tables.

2018-01-23 20:39:17 +00:00

kern

misc: Updates for gcc7.2 for x86

2017-12-14 00:27:59 +00:00

learning_gem5/part2

learning-gem5: Fix missing misc.hh in hello_object.cc

2017-12-05 21:22:37 +00:00

mem

tarch, mem: Abstract the data stored in the SE page tables.

2018-01-23 20:39:17 +00:00

proto

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

python

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

sim

tarch, mem: Abstract the data stored in the SE page tables.

2018-01-23 20:39:17 +00:00

unittest

tests: Turn fbtest into a gtest and move it to src/base.

2017-12-12 19:48:02 +00:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

scons, tests: Fix occasional linking error

2017-12-13 23:57:08 +00:00