arch-x86: Adding clflush, clflushopt, clwb instructions

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/x86/cpuid.cc

@@ -37,6 +37,12 @@ namespace X86ISA {
     enum StandardCpuidFunction {
         VendorAndLargestStdFunc,
         FamilyModelStepping,
+        CacheAndTLB,
+        SerialNumber,
+        CacheParams,
+        MonitorMwait,
+        ThermalPowerMgmt,
+        ExtendedFeatures,
         NumStandardCpuidFuncs
     };
 
@@ -158,6 +164,10 @@ namespace X86ISA {
                 result = CpuidResult(0x00020f51, 0x00000805,
                                      0xe7dbfbff, 0x04000209);
                 break;
+              case ExtendedFeatures:
+                result = CpuidResult(0x00000000, 0x01800000,
+                                     0x00000000, 0x00000000);
+                break;
               default:
                 warn("x86 cpuid family 0x0000: unimplemented function %u",
                     funcNum);

src/arch/x86/isa/decoder/two_byte_opcodes.isa

@@ -800,8 +800,16 @@
                     0x3: Inst::STMXCSR(Md);
                     0x4: xsave();
                     0x5: xrstor();
-                    0x6: Inst::UD2();
-                    0x7: clflush();
+                    0x6: decode LEGACY_DECODEVAL {
+                        0x0: Inst::UD2();
+                        0x1: Inst::CLWB(Mb);
+                        default: Inst::UD2();
+                    }
+                    0x7: decode LEGACY_DECODEVAL {
+                        0x0: Inst::CLFLUSH(Mb);
+                        0x1: Inst::CLFLUSHOPT(Mb);
+                        default: Inst::CLFLUSH(Mb);
+                    }
                 }
             }
             0x7: Inst::IMUL(Gv,Ev);

src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py

@@ -58,6 +58,41 @@ def macroop PREFETCH_T0_P
     ld t0, seg, riprel, disp, dataSize=1, prefetch=True
 };
 
+def macroop CLFLUSH_M
+{
+    clflushopt t0, seg, sib, disp, dataSize=1
+    mfence
+};
+
+def macroop CLFLUSH_P
+{
+    rdip t7
+    clflushopt t0, seg, riprel, disp, dataSize=1
+    mfence
+};
+
+def macroop CLFLUSHOPT_M
+{
+    clflushopt t0, seg, sib, disp, dataSize=1
+};
+
+def macroop CLFLUSHOPT_P
+{
+    rdip t7
+    clflushopt t0, seg, riprel, disp, dataSize=1
+};
+
+def macroop CLWB_M
+{
+    clwb t1, seg, sib, disp, dataSize=1
+};
+
+def macroop CLWB_P
+{
+    rdip t7
+    clwb t1, seg, riprel, disp, dataSize=1
+};
+
 '''
 
 #let {{
@@ -71,6 +106,4 @@ def macroop PREFETCH_T0_P
 #       "GenFault ${new UnimpInstFault}"
 #    class PREFETCHW(Inst):
 #       "GenFault ${new UnimpInstFault}"
-#    class CLFLUSH(Inst):
-#       "GenFault ${new UnimpInstFault}"
 #}};

src/arch/x86/isa/microops/ldstop.isa

@@ -634,6 +634,11 @@ let {{
     ''')
 
     defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
+    defineMicroStoreOp('Clflushopt', 'Mem = 0;',
+                       mem_flags="Request::CLEAN | Request::INVALIDATE" +
+                       " | Request::DST_POC")
+    defineMicroStoreOp('Clwb', 'Mem = 0;',
+                       mem_flags="Request::CLEAN | Request::DST_POC")
 
     def defineMicroStoreSplitOp(mnemonic, code,
                                 completeCode="", mem_flags="0"):