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gem5/src/dev
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Curtis Dunham c3268f8820 config: Support full-system with SST's memory system 
This patch adds an example configuration in ext/sst/tests/ that allows
an SST/gem5 instance to simulate a 4-core AArch64 system with SST's
memHierarchy components providing all the caches and memories.
2015-04-08 15:56:06 -05:00
..
alpha
dev: prevent intel 8254 timer counter events firing before startup
2015-01-06 15:10:22 -07:00
arm
config: Support full-system with SST's memory system
2015-04-08 15:56:06 -05:00
mips
dev: prevent intel 8254 timer counter events firing before startup
2015-01-06 15:10:22 -07:00
sparc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
virtio
dev: Correctly clear interrupts in VirtIO PCI
2015-02-03 14:25:47 -05:00
x86
mem: Clarification of packet crossbar timings
2015-02-11 10:23:47 -05:00
baddev.cc
dev: Include basic devices in NULL ISA build
2014-02-18 05:50:59 -05:00
baddev.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
BadDevice.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
copy_engine_defs.hh
Make commenting on close namespace brackets consistent.
2011-01-03 14:35:43 -08:00
copy_engine.cc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
copy_engine.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
CopyEngine.py
config: Remove redundant explicit setting of default clocks
2013-06-27 05:49:49 -04:00
Device.py
dev: Fix IsaFake's cxx_header setting
2014-03-23 11:11:37 -04:00
disk_image.cc
dev: Fix a bug in the use of seekp/seekg
2013-04-17 08:17:03 -04:00
disk_image.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
DiskImage.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
dma_device.cc
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
dma_device.hh
mem: Split port retry for all different packet classes
2015-03-02 04:00:35 -05:00
etherbus.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
etherbus.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
etherdevice.cc
stats: only consider a formula initialized if there is a formula
2010-06-15 01:18:36 -07:00
etherdevice.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
etherdump.cc
Replace curTick global variable with accessor functions.
2011-01-07 21:50:29 -08:00
etherdump.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
etherint.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
etherint.hh
Devices: Make EtherInts connect in the same way memory ports currently do.
2007-08-16 16:49:02 -04:00
etherlink.cc
dev: Use shared_ptr for EthPacketData
2014-10-16 05:49:46 -04:00
etherlink.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
Ethernet.py
sim: Add the notion of clock domains to all ClockedObjects
2013-06-27 05:49:49 -04:00
etherobject.hh
Devices: Make EtherInts connect in the same way memory ports currently do.
2007-08-16 16:49:02 -04:00
etherpkt.cc
PacketFifo: Get slack out of the EthPacketData structure. This allows
2008-06-17 21:34:27 -07:00
etherpkt.hh
dev: Use shared_ptr for EthPacketData
2014-10-16 05:49:46 -04:00
ethertap.cc
dev: Use shared_ptr for EthPacketData
2014-10-16 05:49:46 -04:00
ethertap.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
i8254xGBe_defs.hh
dev: Add missing inline declarations
2012-11-02 11:32:01 -05:00
i8254xGBe.cc
dev: Fix undefined behaviuor in i8254xGBe
2015-02-16 03:34:35 -05:00
i8254xGBe.hh
dev: Fix undefined behaviuor in i8254xGBe
2015-02-16 03:34:35 -05:00
ide_atareg.h
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00
ide_ctrl.cc
dev: Extend access width for IDE control registers
2015-04-03 11:42:10 -05:00
ide_ctrl.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
ide_disk.cc
ide: Accept the IDLE (0xe3) ATA command.
2014-12-03 03:07:35 -08:00
ide_disk.hh
dev: Fix race conditions in IDE device on newer kernels
2013-10-31 13:41:13 -05:00
ide_wdcreg.h
copyright: clean up copyright blocks
2011-06-02 14:36:35 -07:00
Ide.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
intel_8254_timer.cc
dev: prevent intel 8254 timer counter events firing before startup
2015-01-06 15:10:22 -07:00
intel_8254_timer.hh
dev: prevent intel 8254 timer counter events firing before startup
2015-01-06 15:10:22 -07:00
io_device.cc
mem: Clarification of packet crossbar timings
2015-02-11 10:23:47 -05:00
io_device.hh
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
isa_fake.cc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
isa_fake.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
mc146818.cc
dev: (un)serialize fix for the RTC and RTC Timer Interrupt events
2015-04-03 11:42:10 -05:00
mc146818.hh
dev: prevent RTC events firing before startup
2015-01-03 17:51:48 -06:00
ns_gige_reg.h
X86: Get X86_FS to compile.
2007-09-24 17:39:56 -07:00
ns_gige.cc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
ns_gige.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
Pci.py
dev: seperate legacy io offsets from PCI offset
2014-09-03 07:43:06 -04:00
pciconfigall.cc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
pciconfigall.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
pcidev.cc
mem: Clarification of packet crossbar timings
2015-02-11 10:23:47 -05:00
pcidev.hh
dev: refactor pci config space for sysfs scanning
2014-10-16 05:49:57 -04:00
pcireg.h
dev: refactor pci config space for sysfs scanning
2014-10-16 05:49:57 -04:00
pktfifo.cc
dev: Use shared_ptr for EthPacketData
2014-10-16 05:49:46 -04:00
pktfifo.hh
types: clean up types, especially signed vs unsigned
2009-06-04 23:21:12 -07:00
platform.cc
Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed.
2011-02-23 15:10:49 -06:00
platform.hh
dev: Remove unused system pointer in the Platform base class
2015-02-11 10:23:22 -05:00
Platform.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
ps2.cc
dev: Support translating left and right ALT keys.
2014-12-03 03:06:03 -08:00
ps2.hh
ARM: PS2 encoding fix
2012-06-05 01:23:10 -04:00
rtcreg.h
dev: Clean up MC146818 register (A & B) handling
2013-06-03 12:28:41 +02:00
SConscript
dev: Include basic devices in NULL ISA build
2014-02-18 05:50:59 -05:00
simple_disk.cc
dev: use correct delete operation in SimpleDisk
2012-05-10 18:04:27 -05:00
simple_disk.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
SimpleDisk.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
sinic.cc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
sinic.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
sinicreg.hh
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00
terminal.cc
dev: Refactor terminal<->UART interface to make it more generic
2014-09-20 17:17:50 -04:00
terminal.hh
dev: Refactor terminal<->UART interface to make it more generic
2014-09-20 17:17:50 -04:00
Terminal.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
uart8250.cc
mem: Remove redundant Packet::allocate calls
2014-12-02 06:07:41 -05:00
uart8250.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
uart.cc
dev: Refactor terminal<->UART interface to make it more generic
2014-09-20 17:17:50 -04:00
uart.hh
dev: Refactor terminal<->UART interface to make it more generic
2014-09-20 17:17:50 -04:00
Uart.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00