Harry Chiang fce42880b9 dev: move dprint of reg name before register read/write (#1684) ...

Originally, the debug print for read/write to specific register name
will happen after reg.read() and reg.write(). However, there might be
other debug print or warning inside reg.read(), reg.write() which would
be confusing if this debug log happen after all other debug print inside
reg.read(), reg.write().

Creating this commit to change the order.

2024-10-22 10:12:38 +01:00

..

amdgpu

dev-amdgpu: Deprecate rom and mmio trace params (#1633)

2024-10-07 07:12:07 -07:00

arm

configs, dev, learning-gem5, python, tests: more clarification

2024-08-23 18:02:42 -07:00

hsa

misc: Remove all references to GCN3

2024-01-17 11:11:06 -06:00

i2c

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

lupio

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

mips

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

net

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

pci

dev: Make unknown PCI device writes a warning (#1657)

2024-10-14 08:51:05 -07:00

ps2

dev: add reset wrap mode to mouse.cc (#1149)

2024-05-21 10:55:03 -07:00

qemu

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

riscv

arch-riscv: Fix CLINT mtime reset handling (#1638)

2024-10-08 08:51:20 -07:00

serial

dev: Fix interrupt logic in uart8250 (#1009)

2024-04-17 11:27:39 -07:00

sparc

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

storage

dev: Fix off-by-one in IDE controller PCI register allocation (#824)

2024-02-01 10:14:28 -08:00

virtio

tests: Fix compiler tests (#1678)

2024-10-17 11:19:46 -07:00

x86

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

baddev.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

baddev.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

BadDevice.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

Device.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

dma_device.cc

dev: Warn when resp packet is error in dma port

2023-07-07 07:12:54 +00:00

dma_device.hh

cpu,mem,dev: Use Addr for cacheLineSize

2023-09-20 14:16:46 -07:00

dma_virt_device.cc

misc: Remove AMD license addition

2021-12-11 04:00:56 +00:00

dma_virt_device.hh

misc: Remove AMD license addition

2021-12-11 04:00:56 +00:00

intel_8254_timer.cc

dev,arch-x86: Added softstrobe mode to intel8254 timer (#1447)

2024-08-19 12:21:31 -07:00

intel_8254_timer.hh

dev: Refactor how counters are set up in the 8254 timer.

2022-01-16 03:43:58 +00:00

intpin.hh

fastmodel,dev: Rework the Int*Pin classes with Signal*Port.

2022-12-16 07:19:05 +00:00

IntPin.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

io_device.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

io_device.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

isa_fake.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

isa_fake.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

mc146818.cc

dev: Ignore MC146818 UIP bit / Fix x86 Linux 5.11+ boot

2023-01-17 16:43:10 +00:00

mc146818.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

pixelpump.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

pixelpump.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

platform.cc

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

platform.hh

misc: Adopt the gem5 namespace

2021-07-01 19:08:24 +00:00

Platform.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

reg_bank.hh

dev: move dprint of reg name before register read/write (#1684)

2024-10-22 10:12:38 +01:00

reg_bank.test.cc

dev: RegisterBank addRegistersAt for fragmented reg banks (#902)

2024-03-01 15:32:40 +00:00

ResetPort.py

misc: Run pre-commit run --all-files

2023-11-29 22:06:41 -08:00

rtcreg.h

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

SConscript

dev: add debug flag in register bank. (#386)

2023-11-15 10:04:46 -08:00