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dev: Fix off-by-one in IDE controller PCI register allocation (#824)

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The PCI configuration space is 256 bytes, yet because the
PCI_CONFIG_SIZE macro is 0xff, the final register allocation in the IDE
controller only allocated up to byte 255.

Change-Id: I1aef2cad9df366ee8425edb410037061eb29ae33
This commit is contained in:
kroarty-lanl
2024-02-01 10:14:28 -08:00
committed by GitHub
parent b79fe82e5c
commit 197be3a0dd
1 changed files with 2 additions and 1 deletions
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3
src/dev/storage/ide_ctrl.hh
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@@ -96,7 +96,8 @@ class IdeController : public PciDevice
/* 0x48 */ Register8 udmaControl = {"udma control"};
/* 0x49 */ RegisterRaz raz1 = {"raz1", 1};
/* 0x4a-0x4b */ Register16 udmaTiming = {"udma timing"};
/* 0x4c-... */ RegisterRaz raz2 = {"raz2", PCI_CONFIG_SIZE - 0x4c};
/* 0x4c-... */ RegisterRaz raz2 =
{"raz2", (PCI_CONFIG_SIZE + 1) - 0x4c};
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);