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7b5d8b4e5bc913d35f3be5f5242650140a92df78
gem5/src/arch
History
Roger Chang 7b5d8b4e5b arch-riscv: Add vlenb, vtype and vl in PCState
Change-Id: I7c2aed7dda34a1a449253671d7b86aa615c28464
2023-09-12 13:56:21 +08:00
..
amdgpu
gpu-compute,arch-vega: Implement flat scratch insts
2023-08-26 13:40:12 -05:00
arm
fastmodel: Add option to retry licence server connection.
2023-08-15 10:47:32 +00:00
generic
arch-riscv: Fix clearLoadReservation merge (#81)
2023-07-14 08:48:43 -07:00
isa_parser
arch: Add setRegOperand in VecRegOperand
2023-07-10 22:59:12 +00:00
mips
arch,base,dev,sim: Convert objects to use the HostSocket param type.
2023-04-12 02:18:22 +00:00
null
misc: Replace TARGET_ISA with USE_${ISA} variables.
2022-09-02 10:20:51 +00:00
power
arch-power: Fix reporting traps to GDB
2023-08-17 15:55:04 +01:00
riscv
arch-riscv: Add vlenb, vtype and vl in PCState
2023-09-12 13:56:21 +08:00
sparc
misc: Fix 'unused variable' clang errors with gem5.fast
2023-05-08 22:54:06 +00:00
x86
arch-x86: Fix wrong x86 assembly
2023-09-01 00:26:51 +00:00
micro_asm_test.py
misc: Use python f-strings for string formatting
2023-03-16 09:05:29 +00:00
micro_asm.py
misc: Use python f-strings for string formatting
2023-03-16 09:05:29 +00:00
SConscript
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
SConsopts
misc: Replace TARGET_ISA with USE_${ISA} variables.
2022-09-02 10:20:51 +00:00
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