60dd3c7d05
The old logic was setting up a mask which was covering pretty much the entire register, except for the FPSCR[14:13] and FPSCR[6:5] register fields. Those RES0 fields were treated as WI. We simplify this by explicitly marking them as RES0 at construction time Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>