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Giacomo Travaglini 5a65aae091 arch-arm: Simplify AArch64 decode of unimplemented registers 
Those registers are now handled through the fault callbacks

Change-Id: Id07c4d113260b749c24a895ed6e05f52c9f0eb9d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61689
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-07-29 06:51:11 +00:00
..
arch
arch-arm: Simplify AArch64 decode of unimplemented registers
2022-07-29 06:51:11 +00:00
base
misc: Revert gem5 versioning for develop branch
2022-06-20 19:56:24 +00:00
cpu
cpu-o3: Remove TheISA:: types from forwardOldRegs.
2022-07-27 21:55:47 +00:00
dev
arch-arm: Convert to the new faulting logic
2022-07-29 06:51:11 +00:00
doc
misc: Removed unneeded Doxygen pages
2020-04-25 01:08:38 +00:00
doxygen
base,misc: Add group definitions for newly tagged API in src/base
2020-09-08 22:29:43 +00:00
gpu-compute
gpu-compute: Set LDS and Scratch apertures in FS
2022-07-28 14:10:33 +00:00
kern
misc: Update Dmesg dump for changes to printk in Linux v5.10+.
2022-05-11 13:27:50 +00:00
learning_gem5
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
mem
mem: Update the default HBMCtrl config
2022-07-21 19:44:14 +00:00
proto
proto: Add a missing std:: in protoio.cc.
2022-06-03 07:23:27 +00:00
python
stdlib: Allow set_se_binary_workload to take input parameters
2022-07-26 20:42:04 +00:00
sim
arch: Switch the generic register ABI over to use RegId.
2022-06-19 07:48:14 +00:00
sst
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
systemc
systemc: Use debug trace for TlmBridge
2022-07-07 00:55:33 +00:00
Doxyfile
misc: Revert gem5 versioning for develop branch
2022-06-20 19:56:24 +00:00
SConscript
scons: Update GRPC dependency flag
2022-07-22 01:10:33 +00:00