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arch-arm: Simplify AArch64 decode of unimplemented registers

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Those registers are now handled through the fault callbacks

Change-Id: Id07c4d113260b749c24a895ed6e05f52c9f0eb9d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61689
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-07-19 17:35:07 +01:00
parent d18b915008
commit 5a65aae091
1 changed files with 1 additions and 12 deletions
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13
src/arch/arm/isa/formats/aarch64.isa
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@@ -488,7 +488,7 @@ namespace Aarch64
machInst, MiscRegNum64(op0, op1, crn, crm, op2),
rt, read, full_mnemonic);
} else if (lookUpMiscReg[miscReg].info[MISCREG_IMPLEMENTED]) {
} else {
if (miscReg == MISCREG_NZCV) {
if (read)
return new MrsNZCV64(machInst, rt, miscReg);
@@ -554,17 +554,6 @@ namespace Aarch64
return new Msr64(machInst, miscReg, rt);
}
}
} else if (lookUpMiscReg[miscReg].info[MISCREG_WARN_NOT_FAIL]) {
std::string full_mnem = csprintf("%s %s",
read ? "mrs" : "msr", miscRegName[miscReg]);
return new WarnUnimplemented(read ? "mrs" : "msr",
machInst, full_mnem);
} else {
return new FailUnimplemented(read ? "mrs" : "msr",
machInst,
csprintf("%s %s",
read ? "mrs" : "msr",
miscRegName[miscReg]));
}
}
break;