derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Remove unimplemented flag from release dependant regs

Browse Source 
We are instead just disabling read write permissions at every EL
if a specific release is not implemented

Change-Id: I677649c270a442dcd519339e2f64fb7927bf69cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61688
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-07-20 11:57:36 +01:00
parent b7720a0995
commit d18b915008
1 changed files with 25 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

59
src/arch/arm/regs/misc.cc
View File

@@ -3813,8 +3813,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_CURRENTEL)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_PAN)
.allPrivileges().exceptUserMode()
.implemented(release->has(ArmExtension::FEAT_PAN));
.allPrivileges(release->has(ArmExtension::FEAT_PAN))
.exceptUserMode();
InitReg(MISCREG_UAO)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_NZCV)
@@ -4325,47 +4325,38 @@ ISA::initializeMiscRegMetadata()
.res0(0xffffffff00000000)
.mapsTo(MISCREG_CNTHP_TVAL);
InitReg(MISCREG_CNTHPS_CTL_EL2)
.mon()
.hypSecure()
.res0(0xfffffffffffffff8)
.implemented(sel2_implemented);
.mon(sel2_implemented)
.hypSecure(sel2_implemented)
.res0(0xfffffffffffffff8);
InitReg(MISCREG_CNTHPS_CVAL_EL2)
.mon()
.hypSecure()
.implemented(sel2_implemented);
.mon(sel2_implemented)
.hypSecure(sel2_implemented);
InitReg(MISCREG_CNTHPS_TVAL_EL2)
.mon()
.hypSecure()
.res0(0xffffffff00000000)
.implemented(sel2_implemented);
.mon(sel2_implemented)
.hypSecure(sel2_implemented)
.res0(0xffffffff00000000);
InitReg(MISCREG_CNTHV_CTL_EL2)
.mon()
.mon(vhe_implemented)
.hyp()
.res0(0xfffffffffffffff8)
.implemented(vhe_implemented);
.res0(0xfffffffffffffff8);
InitReg(MISCREG_CNTHV_CVAL_EL2)
.mon()
.hyp()
.implemented(vhe_implemented);
.mon(vhe_implemented)
.hyp(vhe_implemented);
InitReg(MISCREG_CNTHV_TVAL_EL2)
.mon()
.hyp()
.res0(0xffffffff00000000)
.implemented(vhe_implemented);
.mon(vhe_implemented)
.hyp(vhe_implemented)
.res0(0xffffffff00000000);
InitReg(MISCREG_CNTHVS_CTL_EL2)
.mon()
.hypSecure()
.res0(0xfffffffffffffff8)
.implemented(vhe_implemented && sel2_implemented);
.mon(vhe_implemented && sel2_implemented)
.hypSecure(vhe_implemented && sel2_implemented)
.res0(0xfffffffffffffff8);
InitReg(MISCREG_CNTHVS_CVAL_EL2)
.mon()
.hypSecure()
.implemented(vhe_implemented && sel2_implemented);
.mon(vhe_implemented && sel2_implemented)
.hypSecure(vhe_implemented && sel2_implemented);
InitReg(MISCREG_CNTHVS_TVAL_EL2)
.mon()
.hypSecure()
.res0(0xffffffff00000000)
.implemented(vhe_implemented && sel2_implemented);
.mon(vhe_implemented && sel2_implemented)
.hypSecure(vhe_implemented && sel2_implemented)
.res0(0xffffffff00000000);
// ENDIF Armv8.1-VHE
InitReg(MISCREG_CNTVOFF_EL2)
.mon()