Giacomo Travaglini 51aba75539 arch-arm: Remove SWP and SWPB instructions ...

The SWP and SWPB instructions have been removed from AArch32.  It was
previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits,
which are now hardcoded to 0b0000 (SWP and SWPB not implemented)

Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15815
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

2019-01-23 14:08:55 +00:00

..

freebsd

sim-se: add syscalls related to polling

2019-01-22 02:05:48 +00:00

insts

arch-arm: Remove SWP and SWPB instructions

2019-01-23 14:08:55 +00:00

isa

arch-arm: Remove SWP and SWPB instructions

2019-01-23 14:08:55 +00:00

kvm

arm: Stop using the FloatReg and FloatRegBits types.

2019-01-14 21:29:28 +00:00

linux

sim-se: add syscalls related to polling

2019-01-22 02:05:48 +00:00

tracers

arch, cpu: Remove float type accessors.

2018-12-20 19:27:51 +00:00

ArmInterrupts.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

ArmISA.py

arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register

2018-10-01 15:47:55 +00:00

ArmNativeTrace.py

cpu: Put all CPU instruction tracers in a single file

2015-01-25 07:22:17 -05:00

ArmPMU.py

arm: Use the interrupt adaptor in the PMU

2018-09-10 09:57:26 +00:00

ArmSemihosting.py

arch-arm: Add support for semihosting STDIO redirection

2018-05-16 17:20:27 +00:00

ArmSystem.py

arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32

2018-11-07 15:22:43 +00:00

ArmTLB.py

arm, power: Make the python TLB simobjects inherit from BaseTLB.

2018-01-11 09:34:23 +00:00

ccregs.hh

arm: use condition code registers for ARM ISA

2014-04-29 16:05:02 -05:00

decoder.cc

arch-arm: Add Illegal Execution flag to PCState

2018-06-14 13:45:49 +00:00

decoder.hh

isa: Add parameter to pick different decoder inside ISA

2015-10-09 14:50:54 -05:00

faults.cc

arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32

2018-11-07 15:22:43 +00:00

faults.hh

arch-arm: Add missing template declaration

2018-11-28 18:20:39 +00:00

interrupts.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

interrupts.hh

arm: Fix secure state checking in various places

2016-08-02 10:38:02 +01:00

intregs.hh

arm: ISA X31 destination register fix

2014-09-03 07:42:43 -04:00

isa_device.cc

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

isa_device.hh

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

isa_traits.hh

alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

2018-01-10 12:19:54 +00:00

isa.cc

arch: cpu: Stop passing around misc registers by reference.

2019-01-22 21:15:45 +00:00

isa.hh

arch: cpu: Stop passing around misc registers by reference.

2019-01-22 21:15:45 +00:00

kernel_stats.hh

stats: Get rid of some kernel stats related cruft.

2017-09-11 04:58:38 +00:00

locked_mem.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

microcode_rom.hh

arm: include missing file for arm

2009-04-21 15:40:26 -07:00

miscregs_types.hh

arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker

2019-01-09 11:08:38 +00:00

miscregs.cc

dev-arm: Add a GICv3 model

2019-01-10 16:29:30 +00:00

miscregs.hh

dev-arm: Add a GICv3 model

2019-01-10 16:29:30 +00:00

mmapped_ipr.hh

arch: Add support for m5ops using mmapped IPRs

2013-09-30 12:20:43 +02:00

nativetrace.cc

cpu: Added interface for vector reg file

2017-07-05 14:43:49 +00:00

nativetrace.hh

ARM: Add vfpv3 support to native trace.

2011-05-04 20:38:26 -05:00

pagetable.hh

arm: Mark uninitialized new TLB entries as not valid

2016-06-20 15:51:31 +01:00

pmu.cc

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

pmu.hh

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

process.cc

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

process.hh

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

pseudo_inst.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

registers.hh

arm: Get rid of some register type definitions.

2019-01-22 21:12:16 +00:00

remote_gdb.cc

arch-arm: implement the GDB XML target description for ARM

2019-01-22 11:35:12 +00:00

remote_gdb.hh

arch-arm: implement the GDB XML target description for ARM

2019-01-22 11:35:12 +00:00

SConscript

arch-arm: implement the GDB XML target description for ARM

2019-01-22 11:35:12 +00:00

SConsopts

arm: add ARM support to M5

2009-04-05 18:53:15 -07:00

semihosting.cc

arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE

2018-05-16 17:20:27 +00:00

semihosting.hh

arch-arm: clang compilation fixes

2018-11-28 11:45:52 +00:00

stacktrace.cc

style: [patch 1/22] use /r/3648/ to reorganize includes

2016-11-09 14:27:37 -06:00

stacktrace.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

stage2_lookup.cc

arch, arm: Return s1Req upon fault in s2Lookup

2018-11-05 09:56:37 +00:00

stage2_lookup.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

stage2_mmu.cc

arch-arm: Fix missing Request allocation

2018-06-13 09:30:17 +00:00

stage2_mmu.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

system.cc

dev-arm: Add a GICv3 model

2019-01-10 16:29:30 +00:00

system.hh

dev-arm: Add a GICv3 model

2019-01-10 16:29:30 +00:00

table_walker.cc

arch-arm: Correction for address size in EL1&0 translation

2018-09-13 09:08:19 +00:00

table_walker.hh

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

tlb.cc

cpu,arch-arm: Initialise data members

2018-11-28 14:12:35 +00:00

tlb.hh

arch, arm: Effect of AT instructions on descriptor handling

2018-11-05 09:56:17 +00:00

tlbi_op.cc

arch-arm: Distinguish IS TLBI from non-IS

2018-03-23 10:24:24 +00:00

tlbi_op.hh

arch-arm: Distinguish IS TLBI from non-IS

2018-03-23 10:24:24 +00:00

types.hh

arch-arm: BadMode checking if corresponding EL is implemented

2018-06-22 10:52:55 +00:00

utility.cc

arm: Replace MiscReg with RegVal in utility.(hh|cc).

2019-01-23 01:55:53 +00:00

utility.hh

arm: Replace MiscReg with RegVal in utility.(hh|cc).

2019-01-23 01:55:53 +00:00

vtophys.cc

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

vtophys.hh

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00