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arch-arm: Remove SWP and SWPB instructions

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The SWP and SWPB instructions have been removed from AArch32.  It was
previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits,
which are now hardcoded to 0b0000 (SWP and SWPB not implemented)

Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15815
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2019-01-18 17:14:56 +00:00
parent e1ef0270da
commit 51aba75539
5 changed files with 0 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/arch/arm/insts/mem.cc
View File

@@ -77,20 +77,6 @@ MemoryReg::printOffset(std::ostream &os) const
}
}
string
Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
stringstream ss;
printMnemonic(ss);
printIntReg(ss, dest);
ss << ", ";
printIntReg(ss, op1);
ss << ", [";
printIntReg(ss, base);
ss << "]";
return ss.str();
}
string
RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{

17
src/arch/arm/insts/mem.hh
View File

@@ -47,23 +47,6 @@
namespace ArmISA
{
class Swap : public PredOp
{
protected:
IntRegIndex dest;
IntRegIndex op1;
IntRegIndex base;
Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base)
: PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), base(_base)
{}
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
class MightBeMicro : public PredOp
{
protected:

4
src/arch/arm/isa/formats/mem.isa
View File

@@ -226,10 +226,6 @@ def format ArmSyncMem() {{
const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
switch (PUBWL) {
case 0x10:
return new Swp(machInst, rt, rt2, rn);
case 0x14:
return new Swpb(machInst, rt, rt2, rn);
case 0x18:
return new %(strex)s(machInst, rt, rt2, rn, true, 0);
case 0x19:

3
src/arch/arm/isa/insts/insts.isa
View File

@@ -62,9 +62,6 @@ split decoder;
//Stores of a single item
##include "str.isa"
//Swaps
##include "swap.isa"
//Load/store multiple
##include "macromem.isa"

96
src/arch/arm/isa/insts/swap.isa
View File

@@ -1,96 +0,0 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2011 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
let {{
header_output = decoder_output = exec_output = ""
class SwapInst(LoadStoreInst):
execBase = 'Swap'
decConstBase = 'Swap'
def __init__(self, name, Name, eaCode,
preAccCode, postAccCode, memFlags, instFlags = []):
super(SwapInst, self).__init__()
self.name = name
self.Name = Name
self.eaCode = eaCode
self.preAccCode = preAccCode
self.postAccCode = postAccCode
self.memFlags = memFlags
self.instFlags = instFlags
def emit(self):
global header_output, decoder_output, exec_output
codeBlobs = { "ea_code": self.eaCode,
"preacc_code": self.preAccCode,
"postacc_code": self.postAccCode }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
self.memFlags, self.instFlags,
base = 'Swap')
header_output += newHeader
decoder_output += newDecoder
exec_output += newExec
swpPreAccCode = '''
if (!((SCTLR)Sctlr).sw) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
}
'''
SwapInst('swp', 'Swp', 'EA = Base;',
swpPreAccCode + 'Mem = cSwap(Op1_uw, ((CPSR)Cpsr).e);',
'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignWord',
'ArmISA::TLB::MustBeOne'],
['IsStoreConditional']).emit()
SwapInst('swpb', 'Swpb', 'EA = Base;',
swpPreAccCode + 'Mem_ub = cSwap(Op1_ub, ((CPSR)Cpsr).e);',
'Dest_ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignByte',
'ArmISA::TLB::MustBeOne'],
['IsStoreConditional']).emit()
}};