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arch: cpu: Stop passing around misc registers by reference.

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These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.

Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2018-10-18 17:34:08 -07:00
parent 774770a641
commit 230b892fa3
23 changed files with 58 additions and 68 deletions
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5
src/arch/alpha/isa.cc
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@@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
}
void
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -140,8 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
}
void
ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
ThreadID tid)
ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:

7
src/arch/alpha/isa.hh
View File

@@ -77,10 +77,9 @@ namespace AlphaISA
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
ThreadID tid = 0);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc,
ThreadID tid=0);
void
clear()

4
src/arch/arm/isa.cc
View File

@@ -710,7 +710,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
}
void
ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
{
assert(misc_reg < NumMiscRegs);
@@ -732,7 +732,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val)
}
void
ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc)
ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
RegVal newVal = val;

4
src/arch/arm/isa.hh
View File

@@ -430,8 +430,8 @@ namespace ArmISA
public:
RegVal readMiscRegNoEffect(int misc_reg) const;
RegVal readMiscReg(int misc_reg, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, const RegVal &val);
void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, RegVal val);
void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const

9
src/arch/mips/isa.cc
View File

@@ -445,7 +445,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
}
void
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -458,7 +458,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
}
void
ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -473,8 +473,7 @@ ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
// be overwritten. Make sure to handle those particular registers
// with care!
void
ISA::setMiscReg(int misc_reg, const MiscReg &val,
ThreadContext *tc, ThreadID tid)
ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -497,7 +496,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val,
* (setRegWithEffect)
*/
MiscReg
ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
ISA::filterCP0Write(int misc_reg, int reg_sel, MiscReg val)
{
MiscReg retVal = val;

11
src/arch/mips/isa.hh
View File

@@ -94,14 +94,13 @@ namespace MipsISA
MiscReg readMiscReg(int misc_reg,
ThreadContext *tc, ThreadID tid = 0);
MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
ThreadID tid = 0);
MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val);
void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
//template <class TC>
void setMiscReg(int misc_reg, const MiscReg &val,
ThreadContext *tc, ThreadID tid = 0);
void setMiscReg(int misc_reg, MiscReg val,
ThreadContext *tc, ThreadID tid=0);
//////////////////////////////////////////////////////////
//

4
src/arch/power/isa.hh
View File

@@ -76,13 +76,13 @@ class ISA : public SimObject
}
void
setMiscRegNoEffect(int misc_reg, const MiscReg &val)
setMiscRegNoEffect(int misc_reg, MiscReg val)
{
fatal("Power does not currently have any misc regs defined\n");
}
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
{
fatal("Power does not currently have any misc regs defined\n");
}

6
src/arch/riscv/isa.cc
View File

@@ -164,7 +164,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
}
void
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
ISA::setMiscRegNoEffect(int misc_reg, MiscReg val)
{
if (misc_reg > NumMiscRegs || misc_reg < 0) {
// Illegal CSR
@@ -175,7 +175,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
}
void
ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
{
if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
// Ignore writes to HPM counters for now
@@ -200,4 +200,4 @@ RiscvISA::ISA *
RiscvISAParams::create()
{
return new RiscvISA::ISA(this);
}
}

4
src/arch/riscv/isa.hh
View File

@@ -76,8 +76,8 @@ class ISA : public SimObject
MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, MiscReg val);
void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
RegId flattenRegId(const RegId &regId) const { return regId; }
int flattenIntIndex(int reg) const { return reg; }

7
src/arch/sparc/isa.hh
View File

@@ -116,7 +116,7 @@ class ISA : public SimObject
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
void setFSReg(int miscReg, MiscReg val, ThreadContext *tc);
MiscReg readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
@@ -186,9 +186,8 @@ class ISA : public SimObject
MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, const MiscReg val);
void setMiscReg(int miscReg, const MiscReg val,
ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, MiscReg val);
void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const

2
src/arch/sparc/ua2005.cc
View File

@@ -88,7 +88,7 @@ getMiscRegName(RegIndex index)
}
void
ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();

7
src/cpu/checker/cpu.hh
View File

@@ -417,7 +417,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setMiscRegNoEffect(int misc_reg, const RegVal &val)
setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n",
misc_reg);
@@ -426,7 +426,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setMiscReg(int misc_reg, const RegVal &val) override
setMiscReg(int misc_reg, RegVal val) override
{
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n",
misc_reg);
@@ -443,8 +443,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void
setMiscRegOperand(const StaticInst *si, int idx,
const RegVal &val) override
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());

4
src/cpu/checker/thread_context.hh
View File

@@ -348,7 +348,7 @@ class CheckerThreadContext : public ThreadContext
{ return actualTC->readMiscReg(misc_reg); }
void
setMiscRegNoEffect(int misc_reg, const RegVal &val)
setMiscRegNoEffect(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with no effect: %d to both Checker"
" and O3..\n", misc_reg);
@@ -357,7 +357,7 @@ class CheckerThreadContext : public ThreadContext
}
void
setMiscReg(int misc_reg, const RegVal &val)
setMiscReg(int misc_reg, RegVal val)
{
DPRINTF(Checker, "Setting misc reg with effect: %d to both Checker"
" and O3..\n", misc_reg);

4
src/cpu/exec_context.hh
View File

@@ -182,7 +182,7 @@ class ExecContext {
*/
virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
virtual void setMiscRegOperand(const StaticInst *si,
int idx, const RegVal &val) = 0;
int idx, RegVal val) = 0;
/**
* Reads a miscellaneous register, handling any architectural
@@ -194,7 +194,7 @@ class ExecContext {
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
virtual void setMiscReg(int misc_reg, RegVal val) = 0;
/** @} */

7
src/cpu/minor/exec_context.hh
View File

@@ -309,7 +309,7 @@ class ExecContext : public ::ExecContext
}
void
setMiscReg(int misc_reg, const RegVal &val) override
setMiscReg(int misc_reg, RegVal val) override
{
thread.setMiscReg(misc_reg, val);
}
@@ -323,8 +323,7 @@ class ExecContext : public ::ExecContext
}
void
setMiscRegOperand(const StaticInst *si, int idx,
const RegVal &val) override
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());
@@ -431,7 +430,7 @@ class ExecContext : public ::ExecContext
}
void
setRegOtherThread(const RegId &reg, const RegVal &val,
setRegOtherThread(const RegId &reg, RegVal val,
ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID

6
src/cpu/o3/cpu.cc
View File

@@ -1260,16 +1260,14 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
template <class Impl>
void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const RegVal &val, ThreadID tid)
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
{
this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
}
template <class Impl>
void
FullO3CPU<Impl>::setMiscReg(int misc_reg,
const RegVal &val, ThreadID tid)
FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
{
miscRegfileWrites++;
this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));

4
src/cpu/o3/cpu.hh
View File

@@ -390,12 +390,12 @@ class FullO3CPU : public BaseO3CPU
RegVal readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
void setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid);
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const RegVal &val, ThreadID tid);
void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
RegVal readIntReg(PhysRegIdPtr phys_reg);

4
src/cpu/o3/dyn_inst.hh
View File

@@ -146,7 +146,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
* might have as defined by the architecture.
*/
void
setMiscReg(int misc_reg, const RegVal &val)
setMiscReg(int misc_reg, RegVal val)
{
/** Writes to misc. registers are recorded and deferred until the
* commit stage, when updateMiscRegs() is called. First, check if
@@ -182,7 +182,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
* might have as defined by the architecture.
*/
void
setMiscRegOperand(const StaticInst *si, int idx, const RegVal &val)
setMiscRegOperand(const StaticInst *si, int idx, RegVal val)
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isMiscReg());

4
src/cpu/o3/thread_context.hh
View File

@@ -331,11 +331,11 @@ class O3ThreadContext : public ThreadContext
{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
/** Sets a misc. register. */
virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val);
virtual void setMiscRegNoEffect(int misc_reg, RegVal val);
/** Sets a misc. register, including any side-effects the
* write might have as defined by the architecture. */
virtual void setMiscReg(int misc_reg, const RegVal &val);
virtual void setMiscReg(int misc_reg, RegVal val);
virtual RegId flattenRegId(const RegId& regId) const;

4
src/cpu/o3/thread_context_impl.hh
View File

@@ -307,7 +307,7 @@ O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
@@ -317,7 +317,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const RegVal &val)
#endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(int misc_reg, const RegVal &val)
O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());

5
src/cpu/simple/exec_context.hh
View File

@@ -361,8 +361,7 @@ class SimpleExecContext : public ExecContext {
}
void
setMiscRegOperand(const StaticInst *si, int idx,
const RegVal &val) override
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
{
numIntRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -386,7 +385,7 @@ class SimpleExecContext : public ExecContext {
* side effects due to writing that register.
*/
void
setMiscReg(int misc_reg, const RegVal &val) override
setMiscReg(int misc_reg, RegVal val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);

4
src/cpu/simple_thread.hh
View File

@@ -489,13 +489,13 @@ class SimpleThread : public ThreadState
}
void
setMiscRegNoEffect(int misc_reg, const RegVal &val, ThreadID tid = 0)
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0)
{
return isa->setMiscRegNoEffect(misc_reg, val);
}
void
setMiscReg(int misc_reg, const RegVal &val, ThreadID tid = 0)
setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0)
{
return isa->setMiscReg(misc_reg, val, tc);
}

10
src/cpu/thread_context.hh
View File

@@ -278,9 +278,9 @@ class ThreadContext
virtual RegVal readMiscReg(int misc_reg) = 0;
virtual void setMiscRegNoEffect(int misc_reg, const RegVal &val) = 0;
virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0;
virtual void setMiscReg(int misc_reg, const RegVal &val) = 0;
virtual void setMiscReg(int misc_reg, RegVal val) = 0;
virtual RegId flattenRegId(const RegId& regId) const = 0;
@@ -291,7 +291,7 @@ class ThreadContext
}
virtual void
setRegOtherThread(const RegId& misc_reg, const RegVal &val, ThreadID tid)
setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
{
}
@@ -541,10 +541,10 @@ class ProxyThreadContext : public ThreadContext
RegVal readMiscReg(int misc_reg)
{ return actualTC->readMiscReg(misc_reg); }
void setMiscRegNoEffect(int misc_reg, const RegVal &val)
void setMiscRegNoEffect(int misc_reg, RegVal val)
{ return actualTC->setMiscRegNoEffect(misc_reg, val); }
void setMiscReg(int misc_reg, const RegVal &val)
void setMiscReg(int misc_reg, RegVal val)
{ return actualTC->setMiscReg(misc_reg, val); }
RegId flattenRegId(const RegId& regId) const